i2c_fpga.tan.rpt

利用I2c读取E2prom Verilog 代码

; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; i2c:inst4|en[1]           ; i2c:inst4|seg_data[1]      ; clk        ; clk      ; 70           ;
; Total number of failed paths ;                                          ;               ;                                                ;                           ;                            ;            ;          ; 70           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------+----------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; write           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                           ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 79.99 MHz ( period = 12.501 ns )                    ; i2c_test:inst1|counter[0]                                                                                      ; i2c:inst4|writeData_reg[0]    ; clk        ; clk      ; None                        ; None                      ; 1.832 ns                ;
; N/A                                     ; 81.74 MHz ( period = 12.234 ns )                    ; i2c_test:inst1|counter[1]                                                                                      ; i2c:inst4|writeData_reg[1]    ; clk        ; clk      ; None                        ; None                      ; 1.565 ns                ;
; N/A                                     ; 81.81 MHz ( period = 12.224 ns )                    ; i2c_test:inst1|counter[2]                                                                                      ; i2c:inst4|writeData_reg[2]    ; clk        ; clk      ; None                        ; None                      ; 1.555 ns                ;
; N/A                                     ; 82.11 MHz ( period = 12.179 ns )                    ; i2c_test:inst1|counter[3]                                                                                      ; i2c:inst4|writeData_reg[3]    ; clk        ; clk      ; None                        ; None                      ; 1.510 ns                ;
; N/A                                     ; 82.93 MHz ( period = 12.058 ns )                    ; i2c:inst4|inner_state.first                                                                                    ; i2c:inst4|sda_buf             ; clk        ; clk      ; None                        ; None                      ; 11.349 ns               ;
; N/A                                     ; 84.31 MHz ( period = 11.861 ns )                    ; i2c:inst4|inner_state.eighth                                                                                   ; i2c:inst4|sda_buf             ; clk        ; clk      ; None                        ; None                      ; 11.152 ns               ;