vga_wb_master.v.bak

VGA接口协议的硬件描述语言代码

		.nword  ( ),
		.empty  ( ),
		.full   ( ),
		.aempty ( ),
		.afull  ( )
	);


	//
	// generate burst counter
	wire [3:0] burst_cnt_val;
	assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
	assign burst_done = burst_cnt_val[3];

	always @(posedge clk_i)
	  if ( (burst_done & vmem_ack) | !vmem_acc)
	    case (ctrl_vbl) // synopsis full_case parallel_case
	      2'b00: burst_cnt <= #1 3'b000; // burst length 1
	      2'b01: burst_cnt <= #1 3'b001; // burst length 2
	      2'b10: burst_cnt <= #1 3'b011; // burst length 4
	      2'b11: burst_cnt <= #1 3'b111; // burst length 8
	    endcase
	  else if(vmem_ack)
	    burst_cnt <= #1 burst_cnt_val[2:0];

	//
	// generate image counters
	//

	// hgate counter
	reg  [15:0] hgate_cnt;
	reg  [16:0] hgate_cnt_val;
	reg  [1:0]  hgate_div_cnt;
	reg  [2:0]  hgate_div_val;

	wire hdone = hgate_cnt_val[16] & vmem_ack; // ????

	always @(hgate_cnt or hgate_div_cnt or ctrl_cd)
	  begin
	      hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;

	      if (ctrl_cd != 2'b10)
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else if ( hgate_div_val[2] )
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else
	        hgate_cnt_val = {1'b0, hgate_cnt};
	  end

	always @(posedge clk_i)
	  if (sclr)
	    begin
	        case(ctrl_cd) // synopsys full_case parallel_case
	          2'b00: hgate_cnt <= #1 Thgate >> 2; //  8bpp, 4 pixels per cycle
	          2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
	          2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
	          2'b11: hgate_cnt <= #1 Thgate;      // 32bpp, 1 pixel per cycle
	        endcase

	        hgate_div_cnt <= 2'b10;
	    end
	  else if (vmem_ack)
	    if (hdone)
	      begin
	          case(ctrl_cd) // synopsys full_case parallel_case
	            2'b00: hgate_cnt <= #1 Thgate >> 2; //  8bpp, 4 pixels per cycle
	            2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
	            2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
	            2'b11: hgate_cnt <= #1 Thgate;      // 32bpp, 1 pixel per cycle
	          endcase

	          hgate_div_cnt <= 2'b10;
	      end
	    else //if (vmem_ack)
	      begin
	          hgate_cnt <= #1 hgate_cnt_val[15:0];

	          if ( hgate_div_val[2] )
	            hgate_div_cnt <= #1 2'b10;
	          else
	            hgate_div_cnt <= #1 hgate_div_val[1:0];
	      end

	// vgate counter
	reg  [15:0] vgate_cnt;
	wire [16:0] vgate_cnt_val;
	wire        vdone;

	assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
	assign vdone = vgate_cnt_val[16];

	always @(posedge clk_i)
	  if (sclr | ImDoneStrb)
	    vgate_cnt <= #1 Tvgate;
	  else if (hdone)
	    vgate_cnt <= #1 vgate_cnt_val[15:0];

	assign ImDone = hdone & vdone;

	assign ImDoneStrb = ImDone & !dImDone;

	always @(posedge clk_i)
	  begin
	      dImDone <= #1 ImDone;
	      dImDoneStrb <= #1 ImDoneStrb;
	  end

	//
	// generate addresses
	//

	// select video memory base address
	always @(posedge clk_i)
	  if (sclr | dImDoneStrb)
	    if (!sel_VBA)
	      vmemA <= #1 VBAa;
	    else
	      vmemA <= #1 VBAb;
	  else if (vmem_ack)
	    vmemA <= #1 vmemA +30'h1;


	////////////////////////////////////
	// hardware cursor signals section
	//
	always @(posedge clk_i)
	  if (ImDone)
	    cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority

	always @(posedge clk_i)
	if (sclr)
	  begin
	      ld_cursor0 <= #1 1'b0;
	      ld_cursor1 <= #1 1'b0;
	  end
	else
	  begin
	      ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done &  cur_acc_sel));
	      ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
	  end

	// select cursor base address
	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;

	// generate pattern offset
	wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
	assign cur_done = next_cursor_adr[9] & cur_ack;

	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_adr <= #1 9'h0;
	  else if (cur_ack)
	    cursor_adr <= #1 next_cursor_adr;

	// generate cursor buffers write enable signals
	assign cursor1_we = cur_ack & !cur_acc_sel;
	assign cursor0_we = cur_ack &  cur_acc_sel;


	//////////////////////////////
	// generate wishbone signals
	//
	assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
	wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone ||
	                cur_acc & !cur_done;

	always @(posedge clk_i or negedge nrst_i)
	  if (!nrst_i)
	    begin
	        cyc_o <= #1 1'b0;
	        stb_o <= #1 1'b0;
	        sel_o <= #1 4'b1111;
	        cti_o <= #1 3'b000;
	        bte_o <= #1 2'b00;
	        we_o  <= #1 1'b0;
	    end
	  else
	    if (rst_i)
	      begin
	          cyc_o <= #1 1'b0;
	          stb_o <= #1 1'b0;
	          sel_o <= #1 4'b1111;
	          cti_o <= #1 3'b000;
	          bte_o <= #1 2'b00;
	          we_o  <= #1 1'b0;
	      end
	    else
	      begin
	          cyc_o <= #1 wb_cycle;
	          stb_o <= #1 wb_cycle;
	          sel_o <= #1 4'b1111;   // only 32bit accesses are supported

	          if (wb_cycle) begin
	            if (cur_acc)
	              cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
	            else if (ctrl_vbl == 2'b00)
	              cti_o <= #1 3'b000;
	            else if (vmem_ack)
	              cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
	          end else
	            cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010;

	          bte_o <= #1 2'b00;     // linear burst
	          we_o  <= #1 1'b0;      // read only
	      end

	//
	// video-data buffer (temporary store data read from video memory)
	wire [3:0] fb_data_fifo_nword;
	wire       fb_data_fifo_full;

	vga_fifo #(4, 32) data_fifo (
		.clk    ( clk_i              ),
		.aclr   ( 1'b1               ),
		.sclr   ( sclr               ),
		.d      ( dat_i              ),
		.wreq   ( vmem_ack           ),
		.q      ( fb_data_fifo_q     ),
		.rreq   ( fb_data_fifo_rreq  ),
		.nword  ( fb_data_fifo_nword ),
		.empty  ( fb_data_fifo_empty ),
		.full   ( fb_data_fifo_full  ),
		.aempty ( ),
		.afull  ( )
	);

//	assign vmem_req = ~(fb_data_fifo_nword[3] | fb_data_fifo_full);
	assign vmem_req = ~fb_data_fifo_nword[3];

endmodule