📄 tests.v.bak
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/////////////////////////////////////////////////////////////////////
//// ////
//// Tests Library ////
//// ////
//// ////
//// Authors: Rudolf Usselmann, Richard Herveille ////
//// rudi@asics.ws, richard@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: tests.v,v 1.8 2003/05/07 14:39:19 rherveille Exp $
//
// $Date: 2003/05/07 14:39:19 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: tests.v,v $
// Revision 1.8 2003/05/07 14:39:19 rherveille
// Added DVI tests
//
// Revision 1.7 2003/05/07 09:45:28 rherveille
// Numerous updates and added checks
//
// Revision 1.6 2003/03/19 12:20:53 rherveille
// Changed timing section in VGA core, changed testbench accordingly.
// Fixed bug in 'timing check' test.
//
// Revision 1.5 2002/04/20 09:57:55 rherveille
// Changed testbench to reflect modified VGA timing generator.
//
//
//
//
//
task show_errors;
begin
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +--------------------+");
end
endtask
task reg_test;
reg [31:0] data;
reg [31:0] pattern;
integer n;
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Register Test ***");
$display("*****************************************************\n");
// Check reset Values
$display("Testing Reset Values ...");
check( `CTRL, 0, 32'h0000_ffff, "CTRL ");
check( `STAT, 0, 32'h0000_0073, "STAT ");
check( `HTIM, 0, 32'hffff_ffff, "HTIM ");
check( `VTIM, 0, 32'hffff_ffff, "VTIM ");
check( `HVLEN, 0, 32'hffff_ffff, "HVLEN");
check( `VBARA, 0, 32'hffff_ffff, "VBARA");
check( `VBARB, 0, 32'hffff_ffff, "VBARB");
$display("Testing Pattern R/W ...");
for(n=0;n<6;n=n+1)
begin
case(n)
0: pattern = 32'h0000_0000;
1: pattern = 32'hffff_ffff;
2: pattern = 32'haaaa_aaaa;
3: pattern = 32'h5555_5555;
4: pattern = 32'hcccc_cccc;
5: pattern = 32'h3333_3333;
endcase
m0.wb_wr1( `CTRL, 4'hf, pattern );
check( `CTRL, pattern, 32'h0000_ffff, "CTRL ");
m0.wb_wr1( `HTIM, 4'hf, pattern );
check( `HTIM, pattern, 32'hffff_ffff, "HTIM ");
m0.wb_wr1( `VTIM, 4'hf, pattern );
check( `VTIM, pattern, 32'hffff_ffff, "VTIM ");
m0.wb_wr1( `HVLEN, 4'hf, pattern );
check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN");
m0.wb_wr1( `VBARA, 4'hf, pattern );
check( `VBARA, pattern, 32'hffff_fffc, "VBARA");
m0.wb_wr1( `VBARB, 4'hf, pattern );
check( `VBARB, pattern, 32'hffff_fffc, "VBARB");
end
repeat(10) @(posedge clk);
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
endtask
task check;
input [31:0] addr;
input [31:0] edata;
input [31:0] mask;
input [39:0] name;
reg [31:0] data;
begin
m0.wb_rd1( addr, 4'hf, data );
if(( (data & mask) != (edata & mask)) | ((^data) === 1'bx) )
begin
$display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)",
name, edata & mask, data, $time);
error_cnt = error_cnt + 1;
end
end
endtask
task tim_test;
integer mode;
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Timing Test ***");
$display("*****************************************************\n");
s0.fill_mem(0);
repeat(10) @(posedge clk);
m0.wb_wr1( `VBARA, 4'hf, 0 );
m0.wb_wr1( `VBARB, 4'hf, 0 );
mode = 2;
for(mode=0;mode<6;mode=mode+1)
begin
// reset core
scen = 0;
m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000);
repeat(10) @(posedge clk);
$display("Mode: %0d", mode);
case(mode)
0:
begin
thsync = 0;
thgdel = 0;
thgate = 319; // gate = 320
thlen = 345;
tvsync = 0;
tvgdel = 0;
tvgate = 239; // vgate = 240
tvlen = 245;
hpol = 0;
vpol = 0;
cpol = 0;
bpol = 0;
end
1:
begin
thsync = 18;
thgdel = 18;
thgate = 319; // gate = 320
thlen = 390;
tvsync = 18;
tvgdel = 18;
tvgate = 239; // vgate = 240
tvlen = 290;
hpol = 1;
vpol = 0;
cpol = 0;
bpol = 0;
end
2:
begin
thsync = 1;
thgdel = 1;
thgate = 639; // hgate = 640
thlen = 644;
tvsync = 1;
tvgdel = 1;
tvgate = 479; // vgate = 480
tvlen = 484;
hpol = 0;
vpol = 1;
cpol = 0;
bpol = 0;
end
3:
begin
thsync = 0;
thgdel = 2;
thgate = 799; // hgate = 800
thlen = 804;
tvsync = 0;
tvgdel = 2;
tvgate = 599; // vgate = 600
tvlen = 604;
hpol = 0;
vpol = 0;
cpol = 1;
bpol = 0;
end
4:
begin
thsync = 3;
thgdel = 2;
thgate = 799; // hgate = 800
thlen = 807;
tvsync = 2;
tvgdel = 2;
tvgate = 599; // vgate = 600
tvlen = 606;
hpol = 0;
vpol = 0;
cpol = 0;
bpol = 1;
end
5:
begin
thsync = 6;
thgdel = 2;
thgate = 799; // hgate = 800
thlen = 810;
tvsync = 4;
tvgdel = 2;
tvgate = 599; // vgate = 600
tvlen = 608;
hpol = 1;
vpol = 1;
cpol = 1;
bpol = 1;
end
endcase
/*
thsync = 0;
thgdel = 0;
thgate = 64;
thlen = 70;
tvsync = 0;
tvgdel = 0;
tvgate = 64;
tvlen = 70;
hpol = 0;
vpol = 0;
cpol = 0;
bpol = 0;
*/
m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
m0.wb_wr1( `CTRL, 4'hf, {
16'h0,
bpol, cpol,
vpol, hpol,
1'b0, // PC
2'h0, // CD
2'h0, // VBL
2'h0, // Reserved
5'h01 // Bank Switch, INT, VideoEn
});
repeat(2) @(posedge vsync);
scen = 1;
repeat(4) @(posedge vsync);
end
scen = 0;
repeat(10) @(posedge clk);
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
endtask
task pd1_test;
integer mode;
integer n, p, l;
reg [31:0] pn;
reg [31:0] pra, paa, tmp;
reg [23:0] pd;
reg [ 1:0] cd;
reg pc;
reg [31:0] data;
reg [31:0] cbar;
reg [ 7:0] vbl;
reg [ 5:0] delay;
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Pixel Data Test 1 ***");
$display("*****************************************************\n");
m0.wb_wr1( `VBARA, 4'hf, 0 );
m0.wb_wr1( `VBARB, 4'hf, 123456 );
cbar = 32'h0000_0800;
thsync = 0;
thgdel = 0;
thgate = 320;
thlen = 345;
tvsync = 0;
tvgdel = 0;
tvgate = 240;
tvlen = 245;
thsync = 39;
thgdel = 124;
thgate = 646;
thlen = 832;
tvsync = 2;
tvgdel = 25;
tvgate = 484;
tvlen = 520;
thsync = 6;
thgdel = 20;
thgate = 319;
thlen = 390;
tvsync = 1;
tvgdel = 8;
tvgate = 239;
tvlen = 280;
/*
thsync = 0;
thgdel = 0;
thgate = 63;
thlen = 70;
tvsync = 0;
tvgdel = 0;
tvgate = 32;
tvlen = 36;
thsync = 119;
thgdel = 61;
thgate = 805;
thlen = 1038;
tvsync = 5;
tvgdel = 20;
tvgate = 600;
tvlen = 665;
*/
hpol = 0;
vpol = 0;
cpol = 0;
bpol = 0;
m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
mode = 3;
vbl = 1;
delay = 1;
for(delay=0;delay<6;delay=delay+1)
begin
s0.set_delay(delay);
for(vbl=0;vbl<4;vbl=vbl+1)
for(mode=0;mode<4;mode=mode+1)
begin
// -------------------------------
// Turn Off VGA before Mode Change
m0.wb_wr1( `CTRL, 4'hf, {
16'h0, // Reserved
bpol, cpol,
vpol, hpol,
pc, // 1'b0, // PC
cd, // 2'h2, // CD
2'h0, // VBL
1'b0, // CBSWE
1'b0, // VBSWE
1'b0, // CBSIE
1'b0, // VBSIE
1'b0, // HIE
1'b0, // VIE
1'b0 // Video Enable
});
s0.fill_mem(1);
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10) @(posedge clk);
for(n=0;n<512;n=n+1)
begin
//m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
data = s0.mem[ cbar[31:2] + n];
m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
end
repeat(10) @(posedge clk);
`endif
case(mode)
0:
begin
cd = 2'h2;
pc = 1'b0;
end
1:
begin
cd = 2'h0;
pc = 1'b0;
end
2:
begin
cd = 2'h0;
pc = 1'b1;
end
3:
begin
cd = 2'h1;
pc = 1'b0;
end
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