x_dcm_adv_v.h

FPGA设计的SDRAM控制器

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Simprim_x_dcm_adv_x_dcm_adv_v_H
#define H_Simprim_x_dcm_adv_x_dcm_adv_v_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Simprim_x_dcm_adv_x_dcm_adv_v: public HSim__s6 {
public:

  char *t319;
  char *t320;
    HSim__s4 PE[80];
    HSim__s1 SE[24];

    class gPE_5_ : public HSimGenValCtor
    {
    public: 
        gPE_5_();
    };

    class gPE_6_ : public HSimGenValCtor
    {
    public: 
        gPE_6_();
    };

    class gPE_9_ : public HSimGenValCtor
    {
    public: 
        gPE_9_();
    };

    class gPE_10_ : public HSimGenValCtor
    {
    public: 
        gPE_10_();
    };

    class gPE_19_ : public HSimGenValCtor
    {
    public: 
        gPE_19_();
    };

    class gPE_20_ : public HSimGenValCtor
    {
    public: 
        gPE_20_();
    };

    class gPE_21_ : public HSimGenValCtor
    {
    public: 
        gPE_21_();
    };

    class gPE_22_ : public HSimGenValCtor
    {
    public: 
        gPE_22_();
    };

    class gPE_23_ : public HSimGenValCtor
    {
    public: 
        gPE_23_();
    };

    class gPE_24_ : public HSimGenValCtor
    {
    public: 
        gPE_24_();
    };

    class gPE_25_ : public HSimGenValCtor
    {
    public: 
        gPE_25_();
    };

    class gPE_26_ : public HSimGenValCtor
    {
    public: 
        gPE_26_();
    };

    class gPE_27_ : public HSimGenValCtor
    {
    public: 
        gPE_27_();
    };

    class gPE_28_ : public HSimGenValCtor
    {
    public: 
        gPE_28_();
    };

    class gPE_29_ : public HSimGenValCtor
    {
    public: 
        gPE_29_();
    };

    class gPE_32_ : public HSimGenValCtor
    {
    public: 
        gPE_32_();
    };

    class gPE_33_ : public HSimGenValCtor
    {
    public: 
        gPE_33_();
    };

    class gPE_36_ : public HSimGenValCtor
    {
    public: 
        gPE_36_();
    };

    class gPE_37_ : public HSimGenValCtor
    {
    public: 
        gPE_37_();
    };

    class gPE_38_ : public HSimGenValCtor
    {
    public: 
        gPE_38_();
    };

    class gPE_39_ : public HSimGenValCtor
    {
    public: 
        gPE_39_();
    };

    class gPE_47_ : public HSimGenValCtor
    {
    public: 
        gPE_47_();
    };

    class gPE_48_ : public HSimGenValCtor
    {
    public: 
        gPE_48_();
    };

    class gPE_51_ : public HSimGenValCtor
    {
    public: 
        gPE_51_();
    };

    class gPE_52_ : public HSimGenValCtor
    {
    public: 
        gPE_52_();
    };

HSim__s4 C55;
HSim__s4 C58;
HSim__s4 C5b;
HSim__s4 C5e;
HSim__s4 C5h;
    HSim__s1 SA[113];
  char t321;
  char t322;
  char t323;
HSimConstraints *c324;
HSimConstraints *c325;
HSimConstraints *c326;
  char *t327;
    Simprim_x_dcm_adv_x_dcm_adv_v(const char * name);
    ~Simprim_x_dcm_adv_x_dcm_adv_v();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Simprim_x_dcm_adv_x_dcm_adv_v_wiredelay: public HSim__s6 {
public:
  Simprim_x_dcm_adv_x_dcm_adv_v *Arch;
  Simprim_x_dcm_adv_x_dcm_adv_v_wiredelay(const char* name,
    Simprim_x_dcm_adv_x_dcm_adv_v *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Simprim_x_dcm_adv_x_dcm_adv_v_signaldelay: public HSim__s6 {
public:
  Simprim_x_dcm_adv_x_dcm_adv_v *Arch;
  Simprim_x_dcm_adv_x_dcm_adv_v_signaldelay(const char* name,
    Simprim_x_dcm_adv_x_dcm_adv_v *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createSimprim_x_dcm_adv_x_dcm_adv_v(const char *name);

#endif