behave.h

FPGA设计的SDRAM控制器

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Work_mt48lc1m16a1_behave_H
#define H_Work_mt48lc1m16a1_behave_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Work_mt48lc1m16a1_behave: public HSim__s6 {
public:

  char *t629;
  char *t630;
    HSim__s4 PE[24];
    HSim__s1 SE[10];

  HSimEnumType State;
  HSimArrayType Array2xibase;
  HSimArrayType Array2xi;
  HSimBitVectorType Array2xbbase;
  HSimBitVectorType Array2xb;
  HSimBitVectorType Array4xbbase;
  HSimBitVectorType Array4xb;
  HSimArrayType Array2x2bvbase;
  HSimArrayType Array2x2bv;
  HSimArrayType Array4xcbvbase;
  HSimArrayType Array4xcbv;
  HSimArrayType Array_statebase;
  HSimArrayType Array_state;
  char *t631;
    HSim__s1 SA[37];
  char t632;
  char t633;
    Work_mt48lc1m16a1_behave(const char * name);
    ~Work_mt48lc1m16a1_behave();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createWork_mt48lc1m16a1_behave(const char *name);

#endif