📄 vrlgutil.h
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////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ /
// \ \ \/
// \ \ Copyright (c) 2003-2004 Xilinx, Inc.
// / / All Right Reserved.
// /---/ /\
// \ \ / \
// \___\/\___\
////////////////////////////////////////////////////////////////////////////////
#ifndef H_Work_vrlgutil_H
#define H_Work_vrlgutil_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif
#include "std/textio/textio.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
class Work_vrlgutil: public HSim__s6 {
public:
/* subprogram name write */
void Gj(HSim__s7 *process, HSimAccessVar &Vd, const char Eg);
/* subprogram name write */
void Gt(HSim__s7 *process, HSimAccessVar &Vn, const char *Er, const HSimConstraints *constrEr);
/* subprogram name write */
void GD(HSim__s7 *process, HSimAccessVar &Vw, const char *Ey, const HSimConstraints *constrEy, const char EB);
/* subprogram name display */
void GK(HSim__s7 *process, HSimAccessVar &VG, const char EI);
/* subprogram name display */
void GS(HSim__s7 *process, HSimAccessVar &VN, const char *EQ, const HSimConstraints *constrEQ);
/* subprogram name display */
void G11(HSim__s7 *process, HSimAccessVar &VV, const char *EX, const HSimConstraints *constrEX, const char EZ);
/* subprogram name display */
void G19(HSim__s7 *process, HSimAccessVar &V14, const int E17);
/* subprogram name display */
void G1h(HSim__s7 *process, HSimAccessVar &V1c, const char *E1f, const HSimConstraints *constrE1f);
/* subprogram name display */
void G1r(HSim__s7 *process, HSimAccessVar &V1k, const int64 E1p);
/* subprogram name newline */
void G1w(HSim__s7 *process, HSimAccessVar &V1u);
/* subprogram name stop */
void G1z(HSim__s7 *process);
/* subprogram name finish */
void G1C(HSim__s7 *process);
public:
public:
Work_vrlgutil(const HSimString &name);
~Work_vrlgutil();
};
extern Work_vrlgutil *WorkVrlgutil;
#endif
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