xsimf_sdrm_arch.cpp

FPGA设计的SDRAM控制器

static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif
#include "C:/Xilinx91i/vhdl/hdp/nt/ieee/std_logic_1164/std_logic_1164.h"
#include "C:/Xilinx91i/vhdl/hdp/nt/std/textio/textio.h"
#include "C:/Xilinx91i/vhdl/hdp/nt/ieee/vital_timing/vital_timing.h"
#include "C:/Xilinx91i/vhdl/hdp/nt/ieee/vital_primitives/vital_primitives.h"
#include "C:/Xilinx91i/vhdl/hdp/nt/ieee/std_logic_arith/std_logic_arith.h"
#include "isim/simprim.auxlib/vpackage/vpackage.h"
#include "isim/work/mti_pkg/mti_pkg.h"
#include "isim/simprim.auxlib/vcomponents/vcomponents.h"
#include "isim/work/ihdlutil/ihdlutil.h"
#include "isim/work/vrlgutil/vrlgutil.h"
#include "isim/work/mt48lc1m16a1_pkg/mt48lc1m16a1_pkg.h"
#include "isim/unisim.auxlib/vcomponents/vcomponents.h"

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VhdlDesignEntity) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        HSim__s6 * topvh = 0;
        extern HSim__s6 * createWork_f_sdrm_f_sdrm_arch(const char*);
        topvh = createWork_f_sdrm_f_sdrm_arch("f_sdrm");
        topvh->constructPorts();
        topvh->checkTopLevelPortsConstrainted();
        topvh->vhdlArchImplement();
        topvh->architectureInstantiate(cfgvh);
        addChild(topvh);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    IeeeStd_logic_1164=new Ieee_std_logic_1164("std_logic_1164");
    StdTextio=new Std_textio("TEXTIO");
    IeeeVital_timing=new Ieee_vital_timing("VITAL_Timing");
    IeeeVital_primitives=new Ieee_vital_primitives("VITAL_Primitives");
    IeeeStd_logic_arith=new Ieee_std_logic_arith("std_logic_arith");
    SimprimVpackage=new Simprim_vpackage("VPACKAGE");
    WorkMti_pkg=new Work_mti_pkg("mti_pkg");
    SimprimVcomponents=new Simprim_vcomponents("VCOMPONENTS");
    WorkIhdlutil=new Work_ihdlutil("ihdlutil");
    WorkVrlgutil=new Work_vrlgutil("vrlgutil");
    WorkMt48lc1m16a1_pkg=new Work_mt48lc1m16a1_pkg("mt48lc1m16a1_PKG");
    UnisimVcomponents=new Unisim_vcomponents("VCOMPONENTS");
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}