📄 fpga_am.map.rpt
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; |lpm_add_sub:lpm_add_sub_component| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component ; work ;
; |addcore:adder| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component|addcore:adder ; work ;
; |a_csnbuffer:result_node| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node ; work ;
; |MODEM:inst4| ; 29 (29) ; 18 ; 0 ; 0 ; 0 ; 11 (11) ; 5 (5) ; 13 (13) ; 18 (18) ; 0 (0) ; |FPGA_AM_TEST|MODEM:inst4 ; work ;
; |altpll0_200M:inst6| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|altpll0_200M:inst6 ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|altpll0_200M:inst6|altpll:altpll_component ; work ;
; |lAM_FUDU:inst10| ; 91 (0) ; 0 ; 0 ; 0 ; 0 ; 91 (0) ; 0 (0) ; 0 (0) ; 69 (0) ; 0 (0) ; |FPGA_AM_TEST|lAM_FUDU:inst10 ; work ;
; |lpm_mult:lpm_mult_component| ; 91 (0) ; 0 ; 0 ; 0 ; 0 ; 91 (0) ; 0 (0) ; 0 (0) ; 69 (0) ; 0 (0) ; |FPGA_AM_TEST|lAM_FUDU:inst10|lpm_mult:lpm_mult_component ; work ;
; |mult_1sm:auto_generated| ; 91 (91) ; 0 ; 0 ; 0 ; 0 ; 91 (91) ; 0 (0) ; 0 (0) ; 69 (69) ; 0 (0) ; |FPGA_AM_TEST|lAM_FUDU:inst10|lpm_mult:lpm_mult_component|mult_1sm:auto_generated ; work ;
; |lpm_rom0_394:inst9| ; 0 (0) ; 0 ; 3940 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|lpm_rom0_394:inst9 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 3940 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|lpm_rom0_394:inst9|altsyncram:altsyncram_component ; work ;
; |lpm_rom0_394_altsyncram:auto_generated| ; 0 (0) ; 0 ; 3940 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FPGA_AM_TEST|lpm_rom0_394:inst9|altsyncram:altsyncram_component|lpm_rom0_394_altsyncram:auto_generated ; work ;
+---------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------------------+
; CARRIER_ROM:inst3|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ALTSYNCRAM ; M4K ; ROM ; 1024 ; 10 ; -- ; -- ; 10240 ; ../../my_dds/project/source/SIN_ROM.mif ;
; lpm_rom0_394:inst9|altsyncram:altsyncram_component|lpm_rom0_394_altsyncram:auto_generated|ALTSYNCRAM ; M4K ; ROM ; 394 ; 10 ; -- ; -- ; 3940 ; ./source/FPGA_AM_394.mif ;
+------------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 27 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 10 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------+
; Source assignments for FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component|addcore:adder ;
+---------------------------+-------+------+-------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+-------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ;
+---------------------------+-------+------+-------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom0_394:inst9|altsyncram:altsyncram_component|lpm_rom0_394_altsyncram:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+----------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------------------------+
+--------------------------------------------------------------------------------------+
; Source assignments for ADD256:inst12|lpm_add_sub:lpm_add_sub_component|addcore:adder ;
+---------------------------+-------+------+-------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+-------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ;
+---------------------------+-------+------+-------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Source assignments for CARRIER_ROM:inst3|altsyncram:altsyncram_component|altsyncram_u981:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------+
+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+-------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------------------+
; LPM_WIDTH ; 10 ; Signed Integer ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_uke ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AM_MOD:inst14|lpm_mult:lpm_mult_component ;
+------------------------------------------------+----------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+----------+----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 10 ; Signed Integer ;
; LPM_WIDTHB ; 10 ; Signed Integer ;
; LPM_WIDTHP ; 10 ; Signed Integer ;
; LPM_WIDTHR ; 0 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
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