carrier.vhd

来自「基于cyclone系列FPGA的模拟幅度调制的VHDL代码」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY CARRIER IS
PORT( --CARRIER : IN STD_LOGIC ;
      CLK : IN STD_LOGIC ;
      --CLK_DA : OUT STD_LOGIC ; 
      DDS_ADDR : OUT  STD_LOGIC_VECTOR(9 DOWNTO 0) ) ;
END ENTITY CARRIER ;

ARCHITECTURE BUILDING OF CARRIER IS
SIGNAL PHASE_WORD : STD_LOGIC_VECTOR(9 DOWNTO 0)  ;
BEGIN 
  --KEY_WORD <= "0000000100" ;
  --CLK_DA <= CLK ;
   
  DDS : PROCESS(CLK) 
          
          BEGIN
            --IF(CLK'EVENT AND CLK = '0') THEN
             -- DDS_ADDR <= DDS_ADDR + '1' ;
             -- IF(DDS_ADDR = 98) THEN
               -- DDS_ADDR <= "0000000";
              -- END IF ;
          --  END IF ; 
            
          IF(CLK'EVENT AND CLK = '1') THEN
            PHASE_WORD <= PHASE_WORD + "0000010001" ;
         
           END IF ;
          
          
        END PROCESS DDS ;
  DDS_ADDR <= PHASE_WORD ;
        
END ARCHITECTURE BUILDING  ;