carrier.vhd.bak

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY MY_DDS IS
PORT( CLK : IN STD_LOGIC ;
      --CLK_50M : IN STD_LOGIC ;
      CLK_DA : OUT STD_LOGIC ; 
      DDS_ADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ) ;
END ENTITY MY_DDS ;

ARCHITECTURE BUILDING OF MY_DDS IS
SIGNAL PHASE_WORD : STD_LOGIC_VECTOR(9 DOWNTO 0)  ;
BEGIN 
  --KEY_WORD <= "0000000100" ;
  CLK_DA <= CLK ;
   
  DDS : PROCESS(CLK) 
        BEGIN
          IF(CLK'EVENT AND CLK = '1') THEN
            PHASE_WORD <= PHASE_WORD + "0000010001" ;
         
           END IF ;
          
        END PROCESS DDS ;
  DDS_ADDR <= PHASE_WORD ;
        
END ARCHITECTURE BUILDING  ;