top_timesim.vhd

清华大学实验箱自带实验程序

    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => mousedata_syn814,
      ADR1 => mousedata_syn4373,
      ADR2 => mousex(7),
      ADR3 => mousex(8),
      O => mousex_9_FROM
    );
  mousex_9_XUSED : X_BUF
    port map (
      I => mousex_9_FROM,
      O => mousedata_cell136
    );
  mousedata_mousex_reg_9_Q : X_FF
    port map (
      I => mousedata_C20_N63,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_9_FFY_ASYNC_FF_GSR_OR,
      O => mousex(9)
    );
  mousex_9_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_9_FFY_RST
    );
  mousex_9_FFY_ASYNC_FF_GSR_OR_11 : X_OR2
    port map (
      I0 => mousex_9_FFY_RST,
      I1 => GSR,
      O => mousex_9_FFY_ASYNC_FF_GSR_OR
    );
  showdata_C170 : X_LUT4
    generic map(
      INIT => X"88A0"
    )
    port map (
      ADR0 => vcnt(9),
      ADR1 => showdata_syn318,
      ADR2 => showdata_syn337,
      ADR3 => showdata_syn1261,
      O => showdata_n377
    );
  showdata_C171 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => vcnt(7),
      ADR1 => vcnt(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N_vsyncb_FROM
    );
  N_vsyncb_XUSED : X_BUF
    port map (
      I => N_vsyncb_FROM,
      O => showdata_syn1261
    );
  showdata_vsyncb_reg : X_FF
    port map (
      I => showdata_n377,
      CE => VCC,
      CLK => N24,
      SET => N_vsyncb_FFY_ASYNC_FF_GSR_OR,
      RST => GND,
      O => N_vsyncb
    );
  N_vsyncb_FFY_SETOR : X_BUF
    port map (
      I => N_resn,
      O => N_vsyncb_FFY_SET
    );
  N_vsyncb_FFY_ASYNC_FF_GSR_OR_12 : X_OR2
    port map (
      I0 => N_vsyncb_FFY_SET,
      I1 => GSR,
      O => N_vsyncb_FFY_ASYNC_FF_GSR_OR
    );
  showdata_C161 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => showdata_N74,
      ADR2 => VCC,
      ADR3 => showdata_syn1018,
      O => showdata_C21_N3
    );
  showdata_C162 : X_LUT4
    generic map(
      INIT => X"B3FF"
    )
    port map (
      ADR0 => showdata_syn305,
      ADR1 => showdata_syn1261,
      ADR2 => showdata_syn366,
      ADR3 => vcnt(9),
      O => showdata_vcnt_0_FROM
    );
  showdata_vcnt_0_XUSED : X_BUF
    port map (
      I => showdata_vcnt_0_FROM,
      O => showdata_syn1018
    );
  showdata_vcnt_reg_0_Q : X_FF
    port map (
      I => showdata_C21_N3,
      CE => VCC,
      CLK => N24,
      SET => GND,
      RST => showdata_vcnt_0_FFY_ASYNC_FF_GSR_OR,
      O => showdata_vcnt(0)
    );
  showdata_vcnt_0_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => showdata_vcnt_0_FFY_RST
    );
  showdata_vcnt_0_FFY_ASYNC_FF_GSR_OR_13 : X_OR2
    port map (
      I0 => showdata_vcnt_0_FFY_RST,
      I1 => GSR,
      O => showdata_vcnt_0_FFY_ASYNC_FF_GSR_OR
    );
  showdata_C160 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => showdata_syn1018,
      ADR2 => VCC,
      ADR3 => showdata_N75,
      O => showdata_C21_N9
    );
  showdata_C159 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => showdata_N76,
      ADR3 => showdata_syn1018,
      O => showdata_C21_N14
    );
  showdata_vcnt_reg_1_Q : X_FF
    port map (
      I => showdata_C21_N9,
      CE => VCC,
      CLK => N24,
      SET => GND,
      RST => vcnt_2_FFY_ASYNC_FF_GSR_OR,
      O => vcnt(1)
    );
  vcnt_2_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => vcnt_2_FFY_RST
    );
  vcnt_2_FFY_ASYNC_FF_GSR_OR_14 : X_OR2
    port map (
      I0 => vcnt_2_FFY_RST,
      I1 => GSR,
      O => vcnt_2_FFY_ASYNC_FF_GSR_OR
    );
  showdata_vcnt_reg_2_Q : X_FF
    port map (
      I => showdata_C21_N14,
      CE => VCC,
      CLK => N24,
      SET => GND,
      RST => vcnt_2_FFX_ASYNC_FF_GSR_OR,
      O => vcnt(2)
    );
  vcnt_2_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => vcnt_2_FFX_RST
    );
  vcnt_2_FFX_ASYNC_FF_GSR_OR_15 : X_OR2
    port map (
      I0 => vcnt_2_FFX_RST,
      I1 => GSR,
      O => vcnt_2_FFX_ASYNC_FF_GSR_OR
    );
  mousedata_C430 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => mousedata_m2_state(4),
      ADR1 => mousedata_m2_state(0),
      ADR2 => mousedata_syn702,
      ADR3 => mousedata_syn777,
      O => mousedata_syn872_GROM
    );
  mousedata_C323 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => mousedata_syn777,
      ADR2 => VCC,
      ADR3 => mousedata_m2_state(4),
      O => mousedata_syn872_FROM
    );
  mousedata_syn872_YUSED : X_BUF
    port map (
      I => mousedata_syn872_GROM,
      O => mousedata_N356
    );
  mousedata_syn872_XUSED : X_BUF
    port map (
      I => mousedata_syn872_FROM,
      O => mousedata_syn872
    );
  showdata_C158 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => showdata_N77,
      ADR2 => showdata_syn1018,
      ADR3 => VCC,
      O => showdata_C21_N19
    );
  showdata_C157 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => showdata_N78,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => showdata_syn1018,
      O => showdata_C21_N24
    );
  showdata_vcnt_reg_3_Q : X_FF
    port map (
      I => showdata_C21_N19,
      CE => VCC,
      CLK => N24,
      SET => GND,
      RST => vcnt_4_FFY_ASYNC_FF_GSR_OR,
      O => vcnt(3)
    );
  vcnt_4_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => vcnt_4_FFY_RST
    );
  vcnt_4_FFY_ASYNC_FF_GSR_OR_16 : X_OR2
    port map (
      I0 => vcnt_4_FFY_RST,
      I1 => GSR,
      O => vcnt_4_FFY_ASYNC_FF_GSR_OR
    );
  showdata_vcnt_reg_4_Q : X_FF
    port map (
      I => showdata_C21_N24,
      CE => VCC,
      CLK => N24,
      SET => GND,
      RST => vcnt_4_FFX_ASYNC_FF_GSR_OR,
      O => vcnt(4)
    );
  vcnt_4_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => vcnt_4_FFX_RST
    );
  vcnt_4_FFX_ASYNC_FF_GSR_OR_17 : X_OR2
    port map (
      I0 => vcnt_4_FFX_RST,
      I1 => GSR,
      O => vcnt_4_FFX_ASYNC_FF_GSR_OR
    );
  mousedata_C330 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => mousedata_syn962,
      ADR1 => mousedata_syn726,
      ADR2 => mousedata_N435,
      ADR3 => mousedata_syn964,
      O => mousedata_C10_N69
    );
  mousedata_C331 : X_LUT4
    generic map(
      INIT => X"020E"
    )
    port map (
      ADR0 => mousedata_syn953,
      ADR1 => mousedata_m1_state(1),
      ADR2 => mousedata_m1_state(0),
      ADR3 => mousedata_syn834,
      O => mousedata_m1_state_0_FROM
    );
  mousedata_m1_state_0_XUSED : X_BUF
    port map (
      I => mousedata_m1_state_0_FROM,
      O => mousedata_syn964
    );
  mousedata_m1_state_reg_0_Q : X_FF
    port map (
      I => mousedata_C10_N69,
      CE => VCC,
      CLK => N23_BUFGed,
      SET => mousedata_m1_state_0_FFY_ASYNC_FF_GSR_OR,
      RST => GND,
      O => mousedata_m1_state(0)
    );
  mousedata_m1_state_0_FFY_SETOR : X_BUF
    port map (
      I => N_resn,
      O => mousedata_m1_state_0_FFY_SET
    );
  mousedata_m1_state_0_FFY_ASYNC_FF_GSR_OR_18 : X_OR2
    port map (
      I0 => mousedata_m1_state_0_FFY_SET,
      I1 => GSR,
      O => mousedata_m1_state_0_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_C406 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => mousex(6),
      ADR1 => mousex(7),
      ADR2 => mousex(5),
      ADR3 => mousex(4),
      O => mousedata_syn4373_GROM
    );
  mousedata_C401 : X_LUT4
    generic map(
      INIT => X"0404"
    )
    port map (
      ADR0 => mousex(6),
      ADR1 => mousedata_q(5),
      ADR2 => mousex(9),
      ADR3 => VCC,
      O => mousedata_syn4373_FROM
    );
  mousedata_syn4373_YUSED : X_BUF
    port map (
      I => mousedata_syn4373_GROM,
      O => mousedata_syn4381
    );
  mousedata_syn4373_XUSED : X_BUF
    port map (
      I => mousedata_syn4373_FROM,
      O => mousedata_syn4373
    );
  showdata_C156 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => showdata_syn1018,