top_timesim.vhd

清华大学实验箱自带实验程序

      ADR0 => mousedata_cell4,
      ADR1 => mousedata_cell136,
      ADR2 => mousedata_N57,
      ADR3 => VCC,
      O => mousedata_C20_N9
    );
  mousedata_C308 : X_LUT4
    generic map(
      INIT => X"0F0A"
    )
    port map (
      ADR0 => mousedata_N58,
      ADR1 => VCC,
      ADR2 => mousedata_cell136,
      ADR3 => mousedata_cell4,
      O => mousedata_C20_N15
    );
  mousedata_mousex_reg_0_Q : X_FF
    port map (
      I => mousedata_C20_N9,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_1_FFY_ASYNC_FF_GSR_OR,
      O => mousex(0)
    );
  mousex_1_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_1_FFY_RST
    );
  mousex_1_FFY_ASYNC_FF_GSR_OR_0 : X_OR2
    port map (
      I0 => mousex_1_FFY_RST,
      I1 => GSR,
      O => mousex_1_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_mousex_reg_1_Q : X_FF
    port map (
      I => mousedata_C20_N15,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_1_FFX_ASYNC_FF_GSR_OR,
      O => mousex(1)
    );
  mousex_1_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_1_FFX_RST
    );
  mousex_1_FFX_ASYNC_FF_GSR_OR_1 : X_OR2
    port map (
      I0 => mousex_1_FFX_RST,
      I1 => GSR,
      O => mousex_1_FFX_ASYNC_FF_GSR_OR
    );
  clocknum_C31 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => clocknum_count(1),
      ADR3 => clocknum_count(0),
      O => clocknum_N50
    );
  clocknum_count_0_BXMUX : X_INV
    port map (
      I => clocknum_count(0),
      O => clocknum_count_0_BXMUXNOT
    );
  clocknum_count_reg_1_Q : X_FF
    port map (
      I => clocknum_N50,
      CE => VCC,
      CLK => sysclk_BUFGPed,
      SET => GND,
      RST => clocknum_count_0_FFY_ASYNC_FF_GSR_OR,
      O => clocknum_count(1)
    );
  clocknum_count_0_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => clocknum_count_0_FFY_RST
    );
  clocknum_count_0_FFY_ASYNC_FF_GSR_OR_2 : X_OR2
    port map (
      I0 => clocknum_count_0_FFY_RST,
      I1 => GSR,
      O => clocknum_count_0_FFY_ASYNC_FF_GSR_OR
    );
  clocknum_count_reg_0_Q : X_FF
    port map (
      I => clocknum_count_0_BXMUXNOT,
      CE => VCC,
      CLK => sysclk_BUFGPed,
      SET => GND,
      RST => clocknum_count_0_FFX_ASYNC_FF_GSR_OR,
      O => clocknum_count(0)
    );
  clocknum_count_0_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => clocknum_count_0_FFX_RST
    );
  clocknum_count_0_FFX_ASYNC_FF_GSR_OR_3 : X_OR2
    port map (
      I0 => clocknum_count_0_FFX_RST,
      I1 => GSR,
      O => clocknum_count_0_FFX_ASYNC_FF_GSR_OR
    );
  mousedata_C346 : X_LUT4
    generic map(
      INIT => X"3322"
    )
    port map (
      ADR0 => mousedata_N59,
      ADR1 => mousedata_cell136,
      ADR2 => VCC,
      ADR3 => mousedata_cell4,
      O => mousedata_C20_N21
    );
  mousedata_C326 : X_LUT4
    generic map(
      INIT => X"5544"
    )
    port map (
      ADR0 => mousedata_cell4,
      ADR1 => mousedata_N60,
      ADR2 => VCC,
      ADR3 => mousedata_cell136,
      O => mousedata_C20_N27
    );
  mousedata_mousex_reg_2_Q : X_FF
    port map (
      I => mousedata_C20_N21,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_3_FFY_ASYNC_FF_GSR_OR,
      O => mousex(2)
    );
  mousex_3_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_3_FFY_RST
    );
  mousex_3_FFY_ASYNC_FF_GSR_OR_4 : X_OR2
    port map (
      I0 => mousex_3_FFY_RST,
      I1 => GSR,
      O => mousex_3_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_mousex_reg_3_Q : X_FF
    port map (
      I => mousedata_C20_N27,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_3_FFX_ASYNC_FF_GSR_OR,
      O => mousex(3)
    );
  mousex_3_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_3_FFX_RST
    );
  mousex_3_FFX_ASYNC_FF_GSR_OR_5 : X_OR2
    port map (
      I0 => mousex_3_FFX_RST,
      I1 => GSR,
      O => mousex_3_FFX_ASYNC_FF_GSR_OR
    );
  mousedata_C372 : X_LUT4
    generic map(
      INIT => X"3322"
    )
    port map (
      ADR0 => mousedata_N61,
      ADR1 => mousedata_cell136,
      ADR2 => VCC,
      ADR3 => mousedata_cell4,
      O => mousedata_C20_N33
    );
  mousedata_C312 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => mousedata_cell4,
      ADR1 => mousedata_N62,
      ADR2 => mousedata_cell136,
      ADR3 => VCC,
      O => mousedata_C20_N39
    );
  mousedata_mousex_reg_4_Q : X_FF
    port map (
      I => mousedata_C20_N33,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => mousex_5_FFY_ASYNC_FF_GSR_OR,
      RST => GND,
      O => mousex(4)
    );
  mousex_5_FFY_SETOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_5_FFY_SET
    );
  mousex_5_FFY_ASYNC_FF_GSR_OR_6 : X_OR2
    port map (
      I0 => mousex_5_FFY_SET,
      I1 => GSR,
      O => mousex_5_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_mousex_reg_5_Q : X_FF
    port map (
      I => mousedata_C20_N39,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_5_FFX_ASYNC_FF_GSR_OR,
      O => mousex(5)
    );
  mousex_5_FFX_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_5_FFX_RST
    );
  mousex_5_FFX_ASYNC_FF_GSR_OR_7 : X_OR2
    port map (
      I0 => mousex_5_FFX_RST,
      I1 => GSR,
      O => mousex_5_FFX_ASYNC_FF_GSR_OR
    );
  showdata_C167 : X_LUT4
    generic map(
      INIT => X"A888"
    )
    port map (
      ADR0 => hcnt(6),
      ADR1 => hcnt(5),
      ADR2 => hcnt(4),
      ADR3 => hcnt(3),
      O => showdata_syn1309_GROM
    );
  showdata_C149 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => hcnt(7),
      ADR1 => hcnt(6),
      ADR2 => hcnt(5),
      ADR3 => hcnt(4),
      O => showdata_syn1309_FROM
    );
  showdata_syn1309_YUSED : X_BUF
    port map (
      I => showdata_syn1309_GROM,
      O => showdata_syn355
    );
  showdata_syn1309_XUSED : X_BUF
    port map (
      I => showdata_syn1309_FROM,
      O => showdata_syn1309
    );
  mousedata_C368 : X_LUT4
    generic map(
      INIT => X"00EE"
    )
    port map (
      ADR0 => mousedata_N63,
      ADR1 => mousedata_cell4,
      ADR2 => VCC,
      ADR3 => mousedata_cell136,
      O => mousedata_C20_N45
    );
  mousedata_C315 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => mousedata_cell136,
      ADR1 => mousedata_N64,
      ADR2 => mousedata_cell4,
      ADR3 => VCC,
      O => mousedata_C20_N51
    );
  mousedata_mousex_reg_6_Q : X_FF
    port map (
      I => mousedata_C20_N45,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => GND,
      RST => mousex_7_FFY_ASYNC_FF_GSR_OR,
      O => mousex(6)
    );
  mousex_7_FFY_RSTOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_7_FFY_RST
    );
  mousex_7_FFY_ASYNC_FF_GSR_OR_8 : X_OR2
    port map (
      I0 => mousex_7_FFY_RST,
      I1 => GSR,
      O => mousex_7_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_mousex_reg_7_Q : X_FF
    port map (
      I => mousedata_C20_N51,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => mousex_7_FFX_ASYNC_FF_GSR_OR,
      RST => GND,
      O => mousex(7)
    );
  mousex_7_FFX_SETOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_7_FFX_SET
    );
  mousex_7_FFX_ASYNC_FF_GSR_OR_9 : X_OR2
    port map (
      I0 => mousex_7_FFX_SET,
      I1 => GSR,
      O => mousex_7_FFX_ASYNC_FF_GSR_OR
    );
  mousedata_C311 : X_LUT4
    generic map(
      INIT => X"0050"
    )
    port map (
      ADR0 => mousedata_cell136,
      ADR1 => VCC,
      ADR2 => mousedata_N65,
      ADR3 => mousedata_cell4,
      O => mousedata_C20_N56
    );
  mousedata_mousex_reg_8_Q : X_FF
    port map (
      I => mousedata_C20_N56,
      CE => mousedata_N356,
      CLK => N23_BUFGed,
      SET => mousex_8_FFY_ASYNC_FF_GSR_OR,
      RST => GND,
      O => mousex(8)
    );
  mousex_8_FFY_SETOR : X_BUF
    port map (
      I => N_resn,
      O => mousex_8_FFY_SET
    );
  mousex_8_FFY_ASYNC_FF_GSR_OR_10 : X_OR2
    port map (
      I0 => mousex_8_FFY_SET,
      I1 => GSR,
      O => mousex_8_FFY_ASYNC_FF_GSR_OR
    );
  mousedata_C399 : X_LUT4
    generic map(
      INIT => X"00FA"
    )
    port map (
      ADR0 => mousedata_cell4,
      ADR1 => VCC,
      ADR2 => mousedata_N66,
      ADR3 => mousedata_cell136,
      O => mousedata_C20_N63
    );
  mousedata_C400 : X_LUT4