top_timesim.vhd

清华大学实验箱自带实验程序

-- Xilinx Vhdl produced by program ngd2vhdl E.31
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w top.nga top_timesim.vhd 
-- Input file: top.nga
-- Output file: top_timesim.vhd
-- Design name: top
-- Xilinx: d:/Xilinx
-- # of Entities: 1
-- Device: 2s100tq144-5

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity top is
  port (
    sysclk : in STD_LOGIC := 'X'; 
    ps2data : inout STD_LOGIC; 
    vsyncb : out STD_LOGIC; 
    ps2clk : inout STD_LOGIC; 
    resn : in STD_LOGIC := 'X'; 
    hsyncb : out STD_LOGIC; 
    rgb : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end top;

architecture Structure of top is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal mousedata_N356 : STD_LOGIC; 
  signal N23_BUFGed : STD_LOGIC; 
  signal mousedata_N58 : STD_LOGIC; 
  signal mousedata_cell4 : STD_LOGIC; 
  signal mousedata_cell136 : STD_LOGIC; 
  signal mousedata_N57 : STD_LOGIC; 
  signal N_resn : STD_LOGIC; 
  signal sysclk_BUFGPed : STD_LOGIC; 
  signal mousedata_N60 : STD_LOGIC; 
  signal mousedata_N59 : STD_LOGIC; 
  signal mousedata_N62 : STD_LOGIC; 
  signal mousedata_N61 : STD_LOGIC; 
  signal showdata_syn1309 : STD_LOGIC; 
  signal showdata_syn355 : STD_LOGIC; 
  signal mousedata_N64 : STD_LOGIC; 
  signal mousedata_N63 : STD_LOGIC; 
  signal mousedata_N65 : STD_LOGIC; 
  signal mousedata_syn814 : STD_LOGIC; 
  signal mousedata_syn4373 : STD_LOGIC; 
  signal mousedata_N66 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal showdata_syn318 : STD_LOGIC; 
  signal showdata_syn337 : STD_LOGIC; 
  signal showdata_syn1261 : STD_LOGIC; 
  signal N_vsyncb : STD_LOGIC; 
  signal showdata_syn305 : STD_LOGIC; 
  signal showdata_syn366 : STD_LOGIC; 
  signal showdata_N74 : STD_LOGIC; 
  signal showdata_syn1018 : STD_LOGIC; 
  signal showdata_N76 : STD_LOGIC; 
  signal showdata_N75 : STD_LOGIC; 
  signal mousedata_syn777 : STD_LOGIC; 
  signal mousedata_syn702 : STD_LOGIC; 
  signal mousedata_syn872 : STD_LOGIC; 
  signal showdata_N78 : STD_LOGIC; 
  signal showdata_N77 : STD_LOGIC; 
  signal mousedata_syn834 : STD_LOGIC; 
  signal mousedata_syn953 : STD_LOGIC; 
  signal mousedata_N435 : STD_LOGIC; 
  signal mousedata_syn726 : STD_LOGIC; 
  signal mousedata_syn962 : STD_LOGIC; 
  signal mousedata_syn964 : STD_LOGIC; 
  signal mousedata_syn4381 : STD_LOGIC; 
  signal showdata_N80 : STD_LOGIC; 
  signal showdata_N79 : STD_LOGIC; 
  signal N_ps2clk : STD_LOGIC; 
  signal mousedata_syn4360 : STD_LOGIC; 
  signal mousedata_syn4599 : STD_LOGIC; 
  signal mousedata_syn799 : STD_LOGIC; 
  signal mousedata_syn723 : STD_LOGIC; 
  signal mousedata_N254 : STD_LOGIC; 
  signal mousedata_C1103 : STD_LOGIC; 
  signal mousedata_syn4593 : STD_LOGIC; 
  signal mousedata_n2495 : STD_LOGIC; 
  signal mousedata_cell173 : STD_LOGIC; 
  signal showdata_N82 : STD_LOGIC; 
  signal showdata_N81 : STD_LOGIC; 
  signal mousedata_syn718 : STD_LOGIC; 
  signal mousedata_syn728 : STD_LOGIC; 
  signal mousedata_syn4551 : STD_LOGIC; 
  signal showdata_N83 : STD_LOGIC; 
  signal mousedata_syn4339 : STD_LOGIC; 
  signal mousedata_syn4325 : STD_LOGIC; 
  signal mousedata_syn4597 : STD_LOGIC; 
  signal mousedata_syn4498 : STD_LOGIC; 
  signal mousedata_syn761 : STD_LOGIC; 
  signal mousedata_cell92 : STD_LOGIC; 
  signal mousedata_syn724 : STD_LOGIC; 
  signal mousedata_syn994 : STD_LOGIC; 
  signal mousedata_syn719 : STD_LOGIC; 
  signal mousedata_syn4505 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal mousedata_syn4304 : STD_LOGIC; 
  signal mousedata_N438 : STD_LOGIC; 
  signal mousedata_syn4444 : STD_LOGIC; 
  signal mousedata_syn877 : STD_LOGIC; 
  signal mousedata_syn878 : STD_LOGIC; 
  signal mousedata_syn721 : STD_LOGIC; 
  signal mousedata_N280 : STD_LOGIC; 
  signal mousedata_syn4588 : STD_LOGIC; 
  signal mousedata_syn4455 : STD_LOGIC; 
  signal mousedata_N452 : STD_LOGIC; 
  signal mousedata_cell159 : STD_LOGIC; 
  signal mousedata_syn939 : STD_LOGIC; 
  signal mousedata_syn4504 : STD_LOGIC; 
  signal mousedata_syn914 : STD_LOGIC; 
  signal mousedata_syn4518 : STD_LOGIC; 
  signal mousedata_syn4513 : STD_LOGIC; 
  signal mousedata_syn765 : STD_LOGIC; 
  signal mousedata_C774 : STD_LOGIC; 
  signal mousedata_cell32 : STD_LOGIC; 
  signal mousedata_cell33 : STD_LOGIC; 
  signal mousedata_C751 : STD_LOGIC; 
  signal mousedata_C733 : STD_LOGIC; 
  signal mousedata_syn4436 : STD_LOGIC; 
  signal mousedata_syn4598 : STD_LOGIC; 
  signal mousedata_C713 : STD_LOGIC; 
  signal mousedata_syn4503 : STD_LOGIC; 
  signal mousedata_syn4478 : STD_LOGIC; 
  signal mousedata_C691 : STD_LOGIC; 
  signal mousedata_C667 : STD_LOGIC; 
  signal mousedata_syn4487 : STD_LOGIC; 
  signal mousedata_syn4490 : STD_LOGIC; 
  signal N_ps2data : STD_LOGIC; 
  signal mousedata_C14_C3_C1 : STD_LOGIC; 
  signal mousedata_syn1038 : STD_LOGIC; 
  signal mousedata_syn4550 : STD_LOGIC; 
  signal mousedata_syn720 : STD_LOGIC; 
  signal mousedata_C19_N3 : STD_LOGIC; 
  signal mousedata_syn717 : STD_LOGIC; 
  signal clocknum_syn150 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal clocknum_syn202 : STD_LOGIC; 
  signal mousedata_syn4397 : STD_LOGIC; 
  signal mousedata_syn4420 : STD_LOGIC; 
  signal mousedata_syn4318 : STD_LOGIC; 
  signal mousedata_syn4437 : STD_LOGIC; 
  signal mousedata_syn903 : STD_LOGIC; 
  signal mousedata_syn4479 : STD_LOGIC; 
  signal mousedata_syn4484 : STD_LOGIC; 
  signal mousedata_syn906 : STD_LOGIC; 
  signal mousedata_syn4500 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal mousedata_syn912 : STD_LOGIC; 
  signal mousedata_syn1888 : STD_LOGIC; 
  signal C32_IBUFG : STD_LOGIC; 
  signal mousedata_syn4343 : STD_LOGIC; 
  signal mousedata_syn4512 : STD_LOGIC; 
  signal mousedata_syn4496 : STD_LOGIC; 
  signal mousedata_syn928 : STD_LOGIC; 
  signal mousedata_syn4521 : STD_LOGIC; 
  signal mousedata_syn4609 : STD_LOGIC; 
  signal mousedata_syn4526 : STD_LOGIC; 
  signal N24_BUFGed : STD_LOGIC; 
  signal mousedata_syn769 : STD_LOGIC; 
  signal mousedata_syn4353 : STD_LOGIC; 
  signal drawboard_C10_C4_C2_O : STD_LOGIC; 
  signal drawboard_N66 : STD_LOGIC; 
  signal drawboard_N67 : STD_LOGIC; 
  signal drawboard_C10_C6_C2_O : STD_LOGIC; 
  signal drawboard_N68 : STD_LOGIC; 
  signal drawboard_N69 : STD_LOGIC; 
  signal mousedata_syn811 : STD_LOGIC; 
  signal drawboard_C10_C8_C2_O : STD_LOGIC; 
  signal drawboard_N70 : STD_LOGIC; 
  signal drawboard_N71 : STD_LOGIC; 
  signal drawboard_C10_C10_C2_O : STD_LOGIC; 
  signal drawboard_N72 : STD_LOGIC; 
  signal drawboard_N73 : STD_LOGIC; 
  signal mousedata_syn4384 : STD_LOGIC; 
  signal drawboard_N74 : STD_LOGIC; 
  signal drawboard_N75 : STD_LOGIC; 
  signal drawboard_C11_C3_C2_O : STD_LOGIC; 
  signal drawboard_N121 : STD_LOGIC; 
  signal drawboard_N122 : STD_LOGIC; 
  signal mousedata_syn830 : STD_LOGIC; 
  signal drawboard_C11_C5_C2_O : STD_LOGIC; 
  signal drawboard_N123 : STD_LOGIC; 
  signal drawboard_N124 : STD_LOGIC; 
  signal drawboard_C11_C7_C2_O : STD_LOGIC; 
  signal drawboard_N125 : STD_LOGIC; 
  signal drawboard_N126 : STD_LOGIC; 
  signal drawboard_C11_C9_C2_O : STD_LOGIC; 
  signal drawboard_N127 : STD_LOGIC; 
  signal drawboard_N128 : STD_LOGIC; 
  signal drawboard_N129 : STD_LOGIC; 
  signal drawboard_N130 : STD_LOGIC; 
  signal showdata_syn1259 : STD_LOGIC; 
  signal showdata_C13_C4_C1_O : STD_LOGIC; 
  signal showdata_N154 : STD_LOGIC; 
  signal showdata_N155 : STD_LOGIC; 
  signal showdata_syn341 : STD_LOGIC; 
  signal showdata_syn344 : STD_LOGIC; 
  signal showdata_C13_C6_C1_O : STD_LOGIC; 
  signal showdata_N156 : STD_LOGIC; 
  signal showdata_N157 : STD_LOGIC; 
  signal drawback_syn550 : STD_LOGIC; 
  signal drawback_syn551 : STD_LOGIC; 
  signal drawback_syn174 : STD_LOGIC; 
  signal showdata_C13_C8_C1_O : STD_LOGIC; 
  signal showdata_N158 : STD_LOGIC; 
  signal showdata_N159 : STD_LOGIC; 
  signal drawback_syn558 : STD_LOGIC; 
  signal drawback_syn559 : STD_LOGIC; 
  signal drawback_syn175 : STD_LOGIC; 
  signal showdata_C13_C10_C1_O : STD_LOGIC; 
  signal showdata_N160 : STD_LOGIC; 
  signal showdata_N161 : STD_LOGIC; 
  signal drawback_syn141 : STD_LOGIC; 
  signal drawback_syn572 : STD_LOGIC; 
  signal drawback_syn482 : STD_LOGIC; 
  signal showdata_C13_C12_C1_O : STD_LOGIC; 
  signal showdata_N162 : STD_LOGIC; 
  signal showdata_N163 : STD_LOGIC; 
  signal drawboard_syn906 : STD_LOGIC; 
  signal drawboard_syn379 : STD_LOGIC; 
  signal showdata_N164 : STD_LOGIC; 
  signal drawboard_C8_C3_C1_O : STD_LOGIC; 
  signal drawboard_n3 : STD_LOGIC; 
  signal drawboard_C8_C5_C1_O : STD_LOGIC; 
  signal drawboard_C8_C7_C1_O : STD_LOGIC; 
  signal drawboard_C8_C9_C1_O : STD_LOGIC; 
  signal drawboard_C8_C11_C1_O : STD_LOGIC; 
  signal drawboard_N24 : STD_LOGIC; 
  signal showdata_syn1277 : STD_LOGIC; 
  signal drawboard_C9_C3_C1_O : STD_LOGIC; 
  signal drawboard_C9_C5_C1_O : STD_LOGIC; 
  signal drawboard_C9_C7_C1_O : STD_LOGIC; 
  signal drawboard_C9_C9_C1_O : STD_LOGIC; 
  signal drawboard_C9_C11_C1_O : STD_LOGIC; 
  signal drawboard_N42 : STD_LOGIC; 
  signal mousedata_C13_C3_C2_O : STD_LOGIC; 
  signal mousedata_C13_C5_C2_O : STD_LOGIC; 
  signal mousedata_C13_C7_C2_O : STD_LOGIC; 
  signal mousedata_C13_C9_C2_O : STD_LOGIC; 
  signal mousedata_C15_C4_C1_O : STD_LOGIC; 
  signal mousedata_C15_C6_C1_O : STD_LOGIC; 
  signal mousedata_C15_C8_C1_O : STD_LOGIC; 
  signal mousedata_C15_C10_C1_O : STD_LOGIC; 
  signal showdata_C10_C4_C1_O : STD_LOGIC; 
  signal showdata_C10_C6_C1_O : STD_LOGIC; 
  signal showdata_C10_C8_C1_O : STD_LOGIC; 
  signal showdata_C10_C10_C1_O : STD_LOGIC; 
  signal drawboard_syn911 : STD_LOGIC; 
  signal drawboard_syn914 : STD_LOGIC; 
  signal drawboard_syn896 : STD_LOGIC; 
  signal drawboard_syn916 : STD_LOGIC; 
  signal showdata_syn383 : STD_LOGIC; 
  signal drawback_syn542 : STD_LOGIC; 
  signal drawback_syn541 : STD_LOGIC; 
  signal drawback_N181 : STD_LOGIC; 
  signal drawback_syn564 : STD_LOGIC; 
  signal drawback_syn565 : STD_LOGIC; 
  signal drawback_syn575 : STD_LOGIC; 
  signal mousedata_syn916 : STD_LOGIC; 
  signal showdata_syn1278 : STD_LOGIC; 
  signal mousedata_C20_N9 : STD_LOGIC; 
  signal mousedata_C20_N15 : STD_LOGIC; 
  signal mousex_1_FFY_RST : STD_LOGIC; 
  signal mousex_1_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousex_1_FFX_RST : STD_LOGIC; 
  signal mousex_1_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal clocknum_count_0_BXMUXNOT : STD_LOGIC; 
  signal clocknum_N50 : STD_LOGIC; 
  signal clocknum_count_0_FFY_RST : STD_LOGIC; 
  signal clocknum_count_0_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal clocknum_count_0_FFX_RST : STD_LOGIC; 
  signal clocknum_count_0_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousedata_C20_N21 : STD_LOGIC; 
  signal mousedata_C20_N27 : STD_LOGIC; 
  signal mousex_3_FFY_RST : STD_LOGIC; 
  signal mousex_3_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousex_3_FFX_RST : STD_LOGIC; 
  signal mousex_3_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousedata_C20_N33 : STD_LOGIC; 
  signal mousedata_C20_N39 : STD_LOGIC; 
  signal mousex_5_FFY_SET : STD_LOGIC; 
  signal mousex_5_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousex_5_FFX_RST : STD_LOGIC; 
  signal mousex_5_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal showdata_syn1309_GROM : STD_LOGIC; 
  signal showdata_syn1309_FROM : STD_LOGIC; 
  signal mousedata_C20_N45 : STD_LOGIC; 
  signal mousedata_C20_N51 : STD_LOGIC; 
  signal mousex_7_FFY_RST : STD_LOGIC; 
  signal mousex_7_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousex_7_FFX_SET : STD_LOGIC; 
  signal mousex_7_FFX_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousedata_C20_N56 : STD_LOGIC; 
  signal mousex_8_FFY_SET : STD_LOGIC; 
  signal mousex_8_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal mousedata_C20_N63 : STD_LOGIC; 
  signal mousex_9_FROM : STD_LOGIC; 
  signal mousex_9_FFY_RST : STD_LOGIC; 
  signal mousex_9_FFY_ASYNC_FF_GSR_OR : STD_LOGIC; 
  signal showdata_n377 : STD_LOGIC; 
  signal N_vsyncb_FROM : STD_LOGIC;