ads7846.tan.qmsg

四线电阻式触摸屏

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dclk ADS7846a:inst\|cs 14.666 ns register " "Info: tco from clock \"clk\" to destination pin \"dclk\" through register \"ADS7846a:inst\|cs\" is 14.666 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.152 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(0.918 ns) 8.152 ns ADS7846a:inst\|cs 3 REG LC_X14_Y6_N8 3 " "Info: 3: + IC(3.039 ns) + CELL(0.918 ns) = 8.152 ns; Loc. = LC_X14_Y6_N8; Fanout = 3; REG Node = 'ADS7846a:inst\|cs'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.957 ns" { fenpin:inst1|clk2mhz ADS7846a:inst|cs } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.40 % ) " "Info: Total cell delay = 3.375 ns ( 41.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.777 ns ( 58.60 % ) " "Info: Total interconnect delay = 4.777 ns ( 58.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|cs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|cs {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.138 ns + Longest register pin " "Info: + Longest register to pin delay is 6.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADS7846a:inst\|cs 1 REG LC_X14_Y6_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y6_N8; Fanout = 3; REG Node = 'ADS7846a:inst\|cs'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS7846a:inst|cs } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.200 ns) 1.138 ns ADS7846a:inst\|dclk~9 2 COMB LC_X14_Y6_N2 1 " "Info: 2: + IC(0.938 ns) + CELL(0.200 ns) = 1.138 ns; Loc. = LC_X14_Y6_N2; Fanout = 1; COMB Node = 'ADS7846a:inst\|dclk~9'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.138 ns" { ADS7846a:inst|cs ADS7846a:inst|dclk~9 } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.678 ns) + CELL(2.322 ns) 6.138 ns dclk 3 PIN PIN_107 0 " "Info: 3: + IC(2.678 ns) + CELL(2.322 ns) = 6.138 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'dclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { ADS7846a:inst|dclk~9 dclk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 696 872 152 "dclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 41.09 % ) " "Info: Total cell delay = 2.522 ns ( 41.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.616 ns ( 58.91 % ) " "Info: Total interconnect delay = 3.616 ns ( 58.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.138 ns" { ADS7846a:inst|cs ADS7846a:inst|dclk~9 dclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.138 ns" { ADS7846a:inst|cs {} ADS7846a:inst|dclk~9 {} dclk {} } { 0.000ns 0.938ns 2.678ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|cs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|cs {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.138 ns" { ADS7846a:inst|cs ADS7846a:inst|dclk~9 dclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.138 ns" { ADS7846a:inst|cs {} ADS7846a:inst|dclk~9 {} dclk {} } { 0.000ns 0.938ns 2.678ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ADS7846a:inst\|cnt1\[0\] penir clk 5.331 ns register " "Info: th for register \"ADS7846a:inst\|cnt1\[0\]\" (data pin = \"penir\", clock pin = \"clk\") is 5.331 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.239 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(1.294 ns) 8.528 ns fenpin:inst1\|clk1khz 3 REG LC_X12_Y4_N9 14 " "Info: 3: + IC(3.039 ns) + CELL(1.294 ns) = 8.528 ns; Loc. = LC_X12_Y4_N9; Fanout = 14; REG Node = 'fenpin:inst1\|clk1khz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.333 ns" { fenpin:inst1|clk2mhz fenpin:inst1|clk1khz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.793 ns) + CELL(0.918 ns) 13.239 ns ADS7846a:inst\|cnt1\[0\] 4 REG LC_X15_Y9_N0 4 " "Info: 4: + IC(3.793 ns) + CELL(0.918 ns) = 13.239 ns; Loc. = LC_X15_Y9_N0; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt1\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.711 ns" { fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 35.27 % ) " "Info: Total cell delay = 4.669 ns ( 35.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 64.73 % ) " "Info: Total interconnect delay = 8.570 ns ( 64.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.129 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns penir 1 PIN PIN_102 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_102; Fanout = 1; PIN Node = 'penir'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { penir } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 120 360 528 136 "penir" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.356 ns) + CELL(0.200 ns) 5.688 ns ADS7846a:inst\|cnt1\[0\]~134 2 COMB LC_X15_Y9_N7 5 " "Info: 2: + IC(4.356 ns) + CELL(0.200 ns) = 5.688 ns; Loc. = LC_X15_Y9_N7; Fanout = 5; COMB Node = 'ADS7846a:inst\|cnt1\[0\]~134'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.556 ns" { penir ADS7846a:inst|cnt1[0]~134 } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(1.760 ns) 8.129 ns ADS7846a:inst\|cnt1\[0\] 3 REG LC_X15_Y9_N0 4 " "Info: 3: + IC(0.681 ns) + CELL(1.760 ns) = 8.129 ns; Loc. = LC_X15_Y9_N0; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt1\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.441 ns" { ADS7846a:inst|cnt1[0]~134 ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.092 ns ( 38.04 % ) " "Info: Total cell delay = 3.092 ns ( 38.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.037 ns ( 61.96 % ) " "Info: Total interconnect delay = 5.037 ns ( 61.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.129 ns" { penir ADS7846a:inst|cnt1[0]~134 ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.129 ns" { penir {} penir~combout {} ADS7846a:inst|cnt1[0]~134 {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 4.356ns 0.681ns } { 0.000ns 1.132ns 0.200ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.129 ns" { penir ADS7846a:inst|cnt1[0]~134 ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.129 ns" { penir {} penir~combout {} ADS7846a:inst|cnt1[0]~134 {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 4.356ns 0.681ns } { 0.000ns 1.132ns 0.200ns 1.760ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 6 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 18 22:33:39 2009 " "Info: Processing ended: Wed Mar 18 22:33:39 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}