ads7846.tan.qmsg

来自「四线电阻式触摸屏」· QMSG 代码 · 共 16 行 · 第 1/4 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "ADS7846a:inst\|pen " "Warning: Node \"ADS7846a:inst\|pen\" is a latch" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 20 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ADS7846a:inst\|wait_flag " "Warning: Node \"ADS7846a:inst\|wait_flag\" is a latch" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst1\|clk1khz " "Info: Detected ripple clock \"fenpin:inst1\|clk1khz\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 8 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst1\|clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ADS7846a:inst\|state.wait_300ms " "Info: Detected ripple clock \"ADS7846a:inst\|state.wait_300ms\" as buffer" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADS7846a:inst\|state.wait_300ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ADS7846a:inst\|state.reset " "Info: Detected ripple clock \"ADS7846a:inst\|state.reset\" as buffer" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADS7846a:inst\|state.reset" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst1\|clk2mhz " "Info: Detected ripple clock \"fenpin:inst1\|clk2mhz\" as buffer" {  } { { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst1\|clk2mhz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}