ads7846.tan.qmsg

四线电阻式触摸屏

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ADS7846a:inst\|cnt2\[5\] register ADS7846a:inst\|wait_flag 57.02 MHz 17.538 ns Internal " "Info: Clock \"clk\" has Internal fmax of 57.02 MHz between source register \"ADS7846a:inst\|cnt2\[5\]\" and destination register \"ADS7846a:inst\|wait_flag\" (period= 17.538 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.453 ns + Longest register register " "Info: + Longest register to register delay is 4.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADS7846a:inst\|cnt2\[5\] 1 REG LC_X14_Y5_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y5_N9; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt2\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS7846a:inst|cnt2[5] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.014 ns) + CELL(0.200 ns) 3.214 ns ADS7846a:inst\|Equal0~88 2 COMB LC_X14_Y6_N4 6 " "Info: 2: + IC(3.014 ns) + CELL(0.200 ns) = 3.214 ns; Loc. = LC_X14_Y6_N4; Fanout = 6; COMB Node = 'ADS7846a:inst\|Equal0~88'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { ADS7846a:inst|cnt2[5] ADS7846a:inst|Equal0~88 } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 3.948 ns ADS7846a:inst\|Selector13~17 3 COMB LC_X14_Y6_N5 1 " "Info: 3: + IC(0.534 ns) + CELL(0.200 ns) = 3.948 ns; Loc. = LC_X14_Y6_N5; Fanout = 1; COMB Node = 'ADS7846a:inst\|Selector13~17'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { ADS7846a:inst|Equal0~88 ADS7846a:inst|Selector13~17 } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.453 ns ADS7846a:inst\|wait_flag 4 REG LC_X14_Y6_N6 2 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.453 ns; Loc. = LC_X14_Y6_N6; Fanout = 2; REG Node = 'ADS7846a:inst\|wait_flag'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { ADS7846a:inst|Selector13~17 ADS7846a:inst|wait_flag } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.600 ns ( 13.47 % ) " "Info: Total cell delay = 0.600 ns ( 13.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.853 ns ( 86.53 % ) " "Info: Total interconnect delay = 3.853 ns ( 86.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.453 ns" { ADS7846a:inst|cnt2[5] ADS7846a:inst|Equal0~88 ADS7846a:inst|Selector13~17 ADS7846a:inst|wait_flag } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.453 ns" { ADS7846a:inst|cnt2[5] {} ADS7846a:inst|Equal0~88 {} ADS7846a:inst|Selector13~17 {} ADS7846a:inst|wait_flag {} } { 0.000ns 3.014ns 0.534ns 0.305ns } { 0.000ns 0.200ns 0.200ns 0.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.908 ns - Smallest " "Info: - Smallest clock skew is -1.908 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.331 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(1.294 ns) 8.528 ns ADS7846a:inst\|state.reset 3 REG LC_X15_Y9_N5 11 " "Info: 3: + IC(3.039 ns) + CELL(1.294 ns) = 8.528 ns; Loc. = LC_X15_Y9_N5; Fanout = 11; REG Node = 'ADS7846a:inst\|state.reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.333 ns" { fenpin:inst1|clk2mhz ADS7846a:inst|state.reset } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.063 ns) + CELL(0.740 ns) 11.331 ns ADS7846a:inst\|wait_flag 4 REG LC_X14_Y6_N6 2 " "Info: 4: + IC(2.063 ns) + CELL(0.740 ns) = 11.331 ns; Loc. = LC_X14_Y6_N6; Fanout = 2; REG Node = 'ADS7846a:inst\|wait_flag'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { ADS7846a:inst|state.reset ADS7846a:inst|wait_flag } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.491 ns ( 39.63 % ) " "Info: Total cell delay = 4.491 ns ( 39.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.840 ns ( 60.37 % ) " "Info: Total interconnect delay = 6.840 ns ( 60.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.331 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset ADS7846a:inst|wait_flag } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.331 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} ADS7846a:inst|wait_flag {} } { 0.000ns 0.000ns 1.738ns 3.039ns 2.063ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.239 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(1.294 ns) 8.528 ns fenpin:inst1\|clk1khz 3 REG LC_X12_Y4_N9 14 " "Info: 3: + IC(3.039 ns) + CELL(1.294 ns) = 8.528 ns; Loc. = LC_X12_Y4_N9; Fanout = 14; REG Node = 'fenpin:inst1\|clk1khz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.333 ns" { fenpin:inst1|clk2mhz fenpin:inst1|clk1khz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.793 ns) + CELL(0.918 ns) 13.239 ns ADS7846a:inst\|cnt2\[5\] 4 REG LC_X14_Y5_N9 4 " "Info: 4: + IC(3.793 ns) + CELL(0.918 ns) = 13.239 ns; Loc. = LC_X14_Y5_N9; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt2\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.711 ns" { fenpin:inst1|clk1khz ADS7846a:inst|cnt2[5] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 35.27 % ) " "Info: Total cell delay = 4.669 ns ( 35.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 64.73 % ) " "Info: Total interconnect delay = 8.570 ns ( 64.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt2[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt2[5] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.331 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset ADS7846a:inst|wait_flag } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.331 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} ADS7846a:inst|wait_flag {} } { 0.000ns 0.000ns 1.738ns 3.039ns 2.063ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt2[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt2[5] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.032 ns + " "Info: + Micro setup delay of destination is 2.032 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 19 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.453 ns" { ADS7846a:inst|cnt2[5] ADS7846a:inst|Equal0~88 ADS7846a:inst|Selector13~17 ADS7846a:inst|wait_flag } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.453 ns" { ADS7846a:inst|cnt2[5] {} ADS7846a:inst|Equal0~88 {} ADS7846a:inst|Selector13~17 {} ADS7846a:inst|wait_flag {} } { 0.000ns 3.014ns 0.534ns 0.305ns } { 0.000ns 0.200ns 0.200ns 0.200ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.331 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset ADS7846a:inst|wait_flag } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.331 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} ADS7846a:inst|wait_flag {} } { 0.000ns 0.000ns 1.738ns 3.039ns 2.063ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt2[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt2[5] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 5 " "Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ADS7846a:inst\|state.reset ADS7846a:inst\|cnt1\[0\] clk 2.759 ns " "Info: Found hold time violation between source  pin or register \"ADS7846a:inst\|state.reset\" and destination pin or register \"ADS7846a:inst\|cnt1\[0\]\" for clock \"clk\" (Hold time is 2.759 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.087 ns + Largest " "Info: + Largest clock skew is 5.087 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.239 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(1.294 ns) 8.528 ns fenpin:inst1\|clk1khz 3 REG LC_X12_Y4_N9 14 " "Info: 3: + IC(3.039 ns) + CELL(1.294 ns) = 8.528 ns; Loc. = LC_X12_Y4_N9; Fanout = 14; REG Node = 'fenpin:inst1\|clk1khz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.333 ns" { fenpin:inst1|clk2mhz fenpin:inst1|clk1khz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.793 ns) + CELL(0.918 ns) 13.239 ns ADS7846a:inst\|cnt1\[0\] 4 REG LC_X15_Y9_N0 4 " "Info: 4: + IC(3.793 ns) + CELL(0.918 ns) = 13.239 ns; Loc. = LC_X15_Y9_N0; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt1\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.711 ns" { fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 35.27 % ) " "Info: Total cell delay = 4.669 ns ( 35.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 64.73 % ) " "Info: Total interconnect delay = 8.570 ns ( 64.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.152 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 8.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(0.918 ns) 8.152 ns ADS7846a:inst\|state.reset 3 REG LC_X15_Y9_N5 11 " "Info: 3: + IC(3.039 ns) + CELL(0.918 ns) = 8.152 ns; Loc. = LC_X15_Y9_N5; Fanout = 11; REG Node = 'ADS7846a:inst\|state.reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.957 ns" { fenpin:inst1|clk2mhz ADS7846a:inst|state.reset } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.40 % ) " "Info: Total cell delay = 3.375 ns ( 41.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.777 ns ( 58.60 % ) " "Info: Total interconnect delay = 4.777 ns ( 58.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.173 ns - Shortest register register " "Info: - Shortest register to register delay is 2.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADS7846a:inst\|state.reset 1 REG LC_X15_Y9_N5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y9_N5; Fanout = 11; REG Node = 'ADS7846a:inst\|state.reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADS7846a:inst|state.reset } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.930 ns) + CELL(1.243 ns) 2.173 ns ADS7846a:inst\|cnt1\[0\] 2 REG LC_X15_Y9_N0 4 " "Info: 2: + IC(0.930 ns) + CELL(1.243 ns) = 2.173 ns; Loc. = LC_X15_Y9_N0; Fanout = 4; REG Node = 'ADS7846a:inst\|cnt1\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.173 ns" { ADS7846a:inst|state.reset ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.243 ns ( 57.20 % ) " "Info: Total cell delay = 1.243 ns ( 57.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.930 ns ( 42.80 % ) " "Info: Total interconnect delay = 0.930 ns ( 42.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.173 ns" { ADS7846a:inst|state.reset ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.173 ns" { ADS7846a:inst|state.reset {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.930ns } { 0.000ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.239 ns" { clk fenpin:inst1|clk2mhz fenpin:inst1|clk1khz ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.239 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} fenpin:inst1|clk1khz {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.000ns 1.738ns 3.039ns 3.793ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|state.reset } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|state.reset {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.173 ns" { ADS7846a:inst|state.reset ADS7846a:inst|cnt1[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.173 ns" { ADS7846a:inst|state.reset {} ADS7846a:inst|cnt1[0] {} } { 0.000ns 0.930ns } { 0.000ns 1.243ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ADS7846a:inst\|dataoutx\[10\] dout clk -0.390 ns register " "Info: tsu for register \"ADS7846a:inst\|dataoutx\[10\]\" (data pin = \"dout\", clock pin = \"clk\") is -0.390 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.429 ns + Longest pin register " "Info: + Longest pin to register delay is 7.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns dout 1 PIN PIN_103 12 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_103; Fanout = 12; PIN Node = 'dout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 360 528 152 "dout" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.236 ns) + CELL(1.061 ns) 7.429 ns ADS7846a:inst\|dataoutx\[10\] 2 REG LC_X9_Y10_N4 2 " "Info: 2: + IC(5.236 ns) + CELL(1.061 ns) = 7.429 ns; Loc. = LC_X9_Y10_N4; Fanout = 2; REG Node = 'ADS7846a:inst\|dataoutx\[10\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.297 ns" { dout ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 29.52 % ) " "Info: Total cell delay = 2.193 ns ( 29.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.236 ns ( 70.48 % ) " "Info: Total interconnect delay = 5.236 ns ( 70.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.429 ns" { dout ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.429 ns" { dout {} dout~combout {} ADS7846a:inst|dataoutx[10] {} } { 0.000ns 0.000ns 5.236ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.152 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Altera/72/quartus/ads7846/Block1.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns fenpin:inst1\|clk2mhz 2 REG LC_X12_Y3_N6 42 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 42; REG Node = 'fenpin:inst1\|clk2mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk fenpin:inst1|clk2mhz } "NODE_NAME" } } { "fenpin.vhd" "" { Text "D:/Altera/72/quartus/ads7846/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.039 ns) + CELL(0.918 ns) 8.152 ns ADS7846a:inst\|dataoutx\[10\] 3 REG LC_X9_Y10_N4 2 " "Info: 3: + IC(3.039 ns) + CELL(0.918 ns) = 8.152 ns; Loc. = LC_X9_Y10_N4; Fanout = 2; REG Node = 'ADS7846a:inst\|dataoutx\[10\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.957 ns" { fenpin:inst1|clk2mhz ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "ads7846a.vhd" "" { Text "D:/Altera/72/quartus/ads7846/ads7846a.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.40 % ) " "Info: Total cell delay = 3.375 ns ( 41.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.777 ns ( 58.60 % ) " "Info: Total interconnect delay = 4.777 ns ( 58.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|dataoutx[10] {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.429 ns" { dout ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.429 ns" { dout {} dout~combout {} ADS7846a:inst|dataoutx[10] {} } { 0.000ns 0.000ns 5.236ns } { 0.000ns 1.132ns 1.061ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { clk fenpin:inst1|clk2mhz ADS7846a:inst|dataoutx[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { clk {} clk~combout {} fenpin:inst1|clk2mhz {} ADS7846a:inst|dataoutx[10] {} } { 0.000ns 0.000ns 1.738ns 3.039ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}