prev_cmp_gequ.qmsg

梁祝歌曲

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 04 19:42:09 2008 " "Info: Processing started: Sat Oct 04 19:42:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gequ -c gequ " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gequ -c gequ" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gequ.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gequ.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gequ-behavioural " "Info: Found design unit 1: gequ-behavioural" {  } { { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 gequ " "Info: Found entity 1: gequ" {  } { { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv4-behavioural " "Info: Found design unit 1: clockdiv4-behavioural" {  } { { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv4 " "Info: Found entity 1: clockdiv4" {  } { { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file spk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SPK-ONE " "Info: Found design unit 1: SPK-ONE" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 spk " "Info: Found entity 1: spk" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "spk " "Info: Elaborating entity \"spk\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "SPK spk.vhd(26) " "Error (10818): Can't infer register for \"SPK\" at spk.vhd(26) because it does not hold its value outside the clock edge" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 26 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "spk.vhd(26) " "Error (10822): HDL error at spk.vhd(26): couldn't implement registers for assignments on this clock edge" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 26 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Oct 04 19:42:12 2008 " "Error: Processing ended: Sat Oct 04 19:42:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}