prev_cmp_gequ.map.qmsg

梁祝歌曲

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 04 19:42:49 2008 " "Info: Processing started: Sat Oct 04 19:42:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gequ -c gequ " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gequ -c gequ" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gequ.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gequ.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gequ-behavioural " "Info: Found design unit 1: gequ-behavioural" {  } { { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 gequ " "Info: Found entity 1: gequ" {  } { { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdiv4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clockdiv4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clockdiv4-behavioural " "Info: Found design unit 1: clockdiv4-behavioural" {  } { { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clockdiv4 " "Info: Found entity 1: clockdiv4" {  } { { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file spk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SPK-ONE " "Info: Found design unit 1: SPK-ONE" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 spk " "Info: Found entity 1: spk" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "spk " "Info: Elaborating entity \"spk\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "HML\[11\] data_in GND " "Warning (14130): Reduced register \"HML\[11\]\" with stuck data_in port to stuck value GND" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "HML\[10\] data_in GND " "Warning (14130): Reduced register \"HML\[10\]\" with stuck data_in port to stuck value GND" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "HML\[9\] data_in GND " "Warning (14130): Reduced register \"HML\[9\]\" with stuck data_in port to stuck value GND" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "HML\[7\] data_in GND " "Warning (14130): Reduced register \"HML\[7\]\" with stuck data_in port to stuck value GND" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "HML\[3\] data_in GND " "Warning (14130): Reduced register \"HML\[3\]\" with stuck data_in port to stuck value GND" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "SPK~reg0 ss " "Info: Duplicate register \"SPK~reg0\" merged to single register \"ss\", power-up level changed" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 6 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "90 " "Info: Implemented 90 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "87 " "Info: Implemented 87 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 04 19:42:53 2008 " "Info: Processing ended: Sat Oct 04 19:42:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}