gequ.tan.qmsg

梁祝歌曲

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockdiv4:inst\|clock_int " "Info: Detected ripple clock \"clockdiv4:inst\|clock_int\" as buffer" {  } { { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 22 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clockdiv4:inst\|clock_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "gequ:inst1\|clock_int " "Info: Detected ripple clock \"gequ:inst1\|clock_int\" as buffer" {  } { { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 22 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "gequ:inst1\|clock_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "spk:inst5\|sp " "Info: Detected ripple clock \"spk:inst5\|sp\" as buffer" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "spk:inst5\|sp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register spk:inst5\|HML\[2\] register spk:inst5\|DIVIDER\[5\] 93.25 MHz 10.724 ns Internal " "Info: Clock \"clk\" has Internal fmax of 93.25 MHz between source register \"spk:inst5\|HML\[2\]\" and destination register \"spk:inst5\|DIVIDER\[5\]\" (period= 10.724 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.015 ns + Longest register register " "Info: + Longest register to register delay is 10.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spk:inst5\|HML\[2\] 1 REG LC_X16_Y6_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N2; Fanout = 6; REG Node = 'spk:inst5\|HML\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { spk:inst5|HML[2] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.316 ns) + CELL(0.740 ns) 2.056 ns spk:inst5\|Equal6~84 2 COMB LC_X15_Y6_N1 5 " "Info: 2: + IC(1.316 ns) + CELL(0.740 ns) = 2.056 ns; Loc. = LC_X15_Y6_N1; Fanout = 5; COMB Node = 'spk:inst5\|Equal6~84'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.056 ns" { spk:inst5|HML[2] spk:inst5|Equal6~84 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.248 ns) + CELL(0.200 ns) 3.504 ns spk:inst5\|Equal9~93 3 COMB LC_X14_Y6_N5 7 " "Info: 3: + IC(1.248 ns) + CELL(0.200 ns) = 3.504 ns; Loc. = LC_X14_Y6_N5; Fanout = 7; COMB Node = 'spk:inst5\|Equal9~93'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.448 ns" { spk:inst5|Equal6~84 spk:inst5|Equal9~93 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.740 ns) 5.960 ns spk:inst5\|WideOr1~42 4 COMB LC_X15_Y6_N8 2 " "Info: 4: + IC(1.716 ns) + CELL(0.740 ns) = 5.960 ns; Loc. = LC_X15_Y6_N8; Fanout = 2; COMB Node = 'spk:inst5\|WideOr1~42'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.456 ns" { spk:inst5|Equal9~93 spk:inst5|WideOr1~42 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.914 ns) 7.585 ns spk:inst5\|WideOr12~55 5 COMB LC_X15_Y6_N4 4 " "Info: 5: + IC(0.711 ns) + CELL(0.914 ns) = 7.585 ns; Loc. = LC_X15_Y6_N4; Fanout = 4; COMB Node = 'spk:inst5\|WideOr12~55'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { spk:inst5|WideOr1~42 spk:inst5|WideOr12~55 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.839 ns) + CELL(0.591 ns) 10.015 ns spk:inst5\|DIVIDER\[5\] 6 REG LC_X13_Y6_N8 1 " "Info: 6: + IC(1.839 ns) + CELL(0.591 ns) = 10.015 ns; Loc. = LC_X13_Y6_N8; Fanout = 1; REG Node = 'spk:inst5\|DIVIDER\[5\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.430 ns" { spk:inst5|WideOr12~55 spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.185 ns ( 31.80 % ) " "Info: Total cell delay = 3.185 ns ( 31.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.830 ns ( 68.20 % ) " "Info: Total interconnect delay = 6.830 ns ( 68.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.015 ns" { spk:inst5|HML[2] spk:inst5|Equal6~84 spk:inst5|Equal9~93 spk:inst5|WideOr1~42 spk:inst5|WideOr12~55 spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.015 ns" { spk:inst5|HML[2] {} spk:inst5|Equal6~84 {} spk:inst5|Equal9~93 {} spk:inst5|WideOr1~42 {} spk:inst5|WideOr12~55 {} spk:inst5|DIVIDER[5] {} } { 0.000ns 1.316ns 1.248ns 1.716ns 0.711ns 1.839ns } { 0.000ns 0.740ns 0.200ns 0.740ns 0.914ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.632 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv4:inst\|clock_int 2 REG LC_X13_Y3_N3 28 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y3_N3; Fanout = 28; REG Node = 'clockdiv4:inst\|clock_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv4:inst|clock_int } "NODE_NAME" } } { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.519 ns) + CELL(0.918 ns) 8.632 ns spk:inst5\|DIVIDER\[5\] 3 REG LC_X13_Y6_N8 1 " "Info: 3: + IC(3.519 ns) + CELL(0.918 ns) = 8.632 ns; Loc. = LC_X13_Y6_N8; Fanout = 1; REG Node = 'spk:inst5\|DIVIDER\[5\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.437 ns" { clockdiv4:inst|clock_int spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.10 % ) " "Info: Total cell delay = 3.375 ns ( 39.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.257 ns ( 60.90 % ) " "Info: Total interconnect delay = 5.257 ns ( 60.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|DIVIDER[5] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.632 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv4:inst\|clock_int 2 REG LC_X13_Y3_N3 28 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y3_N3; Fanout = 28; REG Node = 'clockdiv4:inst\|clock_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clockdiv4:inst|clock_int } "NODE_NAME" } } { "clockdiv4.vhd" "" { Text "E:/Altera/72/quartus/gequ/clockdiv4.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.519 ns) + CELL(0.918 ns) 8.632 ns spk:inst5\|HML\[2\] 3 REG LC_X16_Y6_N2 6 " "Info: 3: + IC(3.519 ns) + CELL(0.918 ns) = 8.632 ns; Loc. = LC_X16_Y6_N2; Fanout = 6; REG Node = 'spk:inst5\|HML\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.437 ns" { clockdiv4:inst|clock_int spk:inst5|HML[2] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.10 % ) " "Info: Total cell delay = 3.375 ns ( 39.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.257 ns ( 60.90 % ) " "Info: Total interconnect delay = 5.257 ns ( 60.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|HML[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|HML[2] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|DIVIDER[5] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|HML[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|HML[2] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.015 ns" { spk:inst5|HML[2] spk:inst5|Equal6~84 spk:inst5|Equal9~93 spk:inst5|WideOr1~42 spk:inst5|WideOr12~55 spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.015 ns" { spk:inst5|HML[2] {} spk:inst5|Equal6~84 {} spk:inst5|Equal9~93 {} spk:inst5|WideOr1~42 {} spk:inst5|WideOr12~55 {} spk:inst5|DIVIDER[5] {} } { 0.000ns 1.316ns 1.248ns 1.716ns 0.711ns 1.839ns } { 0.000ns 0.740ns 0.200ns 0.740ns 0.914ns 0.591ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|DIVIDER[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|DIVIDER[5] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.632 ns" { clk clockdiv4:inst|clock_int spk:inst5|HML[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.632 ns" { clk {} clk~combout {} clockdiv4:inst|clock_int {} spk:inst5|HML[2] {} } { 0.000ns 0.000ns 1.738ns 3.519ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk spk spk:inst5\|ss 15.733 ns register " "Info: tco from clock \"clk\" to destination pin \"spk\" through register \"spk:inst5\|ss\" is 15.733 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.294 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { { 96 24 192 112 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns gequ:inst1\|clock_int 2 REG LC_X12_Y3_N4 16 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N4; Fanout = 16; REG Node = 'gequ:inst1\|clock_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk gequ:inst1|clock_int } "NODE_NAME" } } { "gequ.vhd" "" { Text "E:/Altera/72/quartus/gequ/gequ.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(1.294 ns) 8.512 ns spk:inst5\|sp 3 REG LC_X12_Y7_N8 1 " "Info: 3: + IC(3.023 ns) + CELL(1.294 ns) = 8.512 ns; Loc. = LC_X12_Y7_N8; Fanout = 1; REG Node = 'spk:inst5\|sp'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.317 ns" { gequ:inst1|clock_int spk:inst5|sp } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.864 ns) + CELL(0.918 ns) 10.294 ns spk:inst5\|ss 4 REG LC_X12_Y7_N6 2 " "Info: 4: + IC(0.864 ns) + CELL(0.918 ns) = 10.294 ns; Loc. = LC_X12_Y7_N6; Fanout = 2; REG Node = 'spk:inst5\|ss'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.782 ns" { spk:inst5|sp spk:inst5|ss } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 45.36 % ) " "Info: Total cell delay = 4.669 ns ( 45.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.625 ns ( 54.64 % ) " "Info: Total interconnect delay = 5.625 ns ( 54.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.294 ns" { clk gequ:inst1|clock_int spk:inst5|sp spk:inst5|ss } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.294 ns" { clk {} clk~combout {} gequ:inst1|clock_int {} spk:inst5|sp {} spk:inst5|ss {} } { 0.000ns 0.000ns 1.738ns 3.023ns 0.864ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.063 ns + Longest register pin " "Info: + Longest register to pin delay is 5.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spk:inst5\|ss 1 REG LC_X12_Y7_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N6; Fanout = 2; REG Node = 'spk:inst5\|ss'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { spk:inst5|ss } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.741 ns) + CELL(2.322 ns) 5.063 ns spk 2 PIN PIN_52 0 " "Info: 2: + IC(2.741 ns) + CELL(2.322 ns) = 5.063 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'spk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.063 ns" { spk:inst5|ss spk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/Altera/72/quartus/gequ/Block1.bdf" { { 96 632 808 112 "spk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 45.86 % ) " "Info: Total cell delay = 2.322 ns ( 45.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.741 ns ( 54.14 % ) " "Info: Total interconnect delay = 2.741 ns ( 54.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.063 ns" { spk:inst5|ss spk } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.063 ns" { spk:inst5|ss {} spk {} } { 0.000ns 2.741ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.294 ns" { clk gequ:inst1|clock_int spk:inst5|sp spk:inst5|ss } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.294 ns" { clk {} clk~combout {} gequ:inst1|clock_int {} spk:inst5|sp {} spk:inst5|ss {} } { 0.000ns 0.000ns 1.738ns 3.023ns 0.864ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.063 ns" { spk:inst5|ss spk } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.063 ns" { spk:inst5|ss {} spk {} } { 0.000ns 2.741ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 13 20:24:24 2008 " "Info: Processing ended: Mon Oct 13 20:24:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}