prev_cmp_gequ.tan.qmsg

梁祝歌曲

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_4HZ register HML\[1\] register DIVIDER\[8\] 93.07 MHz 10.745 ns Internal " "Info: Clock \"CLK_4HZ\" has Internal fmax of 93.07 MHz between source register \"HML\[1\]\" and destination register \"DIVIDER\[8\]\" (period= 10.745 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.036 ns + Longest register register " "Info: + Longest register to register delay is 10.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HML\[1\] 1 REG LC_X13_Y6_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y6_N0; Fanout = 6; REG Node = 'HML\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { HML[1] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.124 ns) + CELL(0.511 ns) 2.635 ns Equal6~84 2 COMB LC_X13_Y7_N1 5 " "Info: 2: + IC(2.124 ns) + CELL(0.511 ns) = 2.635 ns; Loc. = LC_X13_Y7_N1; Fanout = 5; COMB Node = 'Equal6~84'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.635 ns" { HML[1] Equal6~84 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.268 ns) + CELL(0.511 ns) 4.414 ns Equal6~85 3 COMB LC_X14_Y7_N9 6 " "Info: 3: + IC(1.268 ns) + CELL(0.511 ns) = 4.414 ns; Loc. = LC_X14_Y7_N9; Fanout = 6; COMB Node = 'Equal6~85'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.779 ns" { Equal6~84 Equal6~85 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.754 ns) + CELL(0.740 ns) 5.908 ns WideOr9~28 4 COMB LC_X14_Y7_N6 2 " "Info: 4: + IC(0.754 ns) + CELL(0.740 ns) = 5.908 ns; Loc. = LC_X14_Y7_N6; Fanout = 2; COMB Node = 'WideOr9~28'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { Equal6~85 WideOr9~28 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.511 ns) 7.654 ns WideNor0~122 5 COMB LC_X13_Y7_N9 3 " "Info: 5: + IC(1.235 ns) + CELL(0.511 ns) = 7.654 ns; Loc. = LC_X13_Y7_N9; Fanout = 3; COMB Node = 'WideNor0~122'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.746 ns" { WideOr9~28 WideNor0~122 } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.791 ns) + CELL(0.591 ns) 10.036 ns DIVIDER\[8\] 6 REG LC_X10_Y7_N7 1 " "Info: 6: + IC(1.791 ns) + CELL(0.591 ns) = 10.036 ns; Loc. = LC_X10_Y7_N7; Fanout = 1; REG Node = 'DIVIDER\[8\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.382 ns" { WideNor0~122 DIVIDER[8] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.864 ns ( 28.54 % ) " "Info: Total cell delay = 2.864 ns ( 28.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.172 ns ( 71.46 % ) " "Info: Total interconnect delay = 7.172 ns ( 71.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.036 ns" { HML[1] Equal6~84 Equal6~85 WideOr9~28 WideNor0~122 DIVIDER[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.036 ns" { HML[1] {} Equal6~84 {} Equal6~85 {} WideOr9~28 {} WideNor0~122 {} DIVIDER[8] {} } { 0.000ns 2.124ns 1.268ns 0.754ns 1.235ns 1.791ns } { 0.000ns 0.511ns 0.511ns 0.740ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4HZ destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_4HZ\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK_4HZ 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'CLK_4HZ'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_4HZ } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns DIVIDER\[8\] 2 REG LC_X10_Y7_N7 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y7_N7; Fanout = 1; REG Node = 'DIVIDER\[8\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { CLK_4HZ DIVIDER[8] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ DIVIDER[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} DIVIDER[8] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4HZ source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"CLK_4HZ\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK_4HZ 1 CLK PIN_18 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 27; CLK Node = 'CLK_4HZ'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_4HZ } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns HML\[1\] 2 REG LC_X13_Y6_N0 6 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X13_Y6_N0; Fanout = 6; REG Node = 'HML\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { CLK_4HZ HML[1] } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ HML[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} HML[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ DIVIDER[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} DIVIDER[8] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ HML[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} HML[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.036 ns" { HML[1] Equal6~84 Equal6~85 WideOr9~28 WideNor0~122 DIVIDER[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.036 ns" { HML[1] {} Equal6~84 {} Equal6~85 {} WideOr9~28 {} WideNor0~122 {} DIVIDER[8] {} } { 0.000ns 2.124ns 1.268ns 0.754ns 1.235ns 1.791ns } { 0.000ns 0.511ns 0.511ns 0.740ns 0.511ns 0.591ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ DIVIDER[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} DIVIDER[8] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { CLK_4HZ HML[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { CLK_4HZ {} CLK_4HZ~combout {} HML[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_6MHZ SPK ss 10.678 ns register " "Info: tco from clock \"clk_6MHZ\" to destination pin \"SPK\" through register \"ss\" is 10.678 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_6MHZ source 7.212 ns + Longest register " "Info: + Longest clock path from clock \"clk_6MHZ\" to source register is 7.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_6MHZ 1 CLK PIN_20 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 15; CLK Node = 'clk_6MHZ'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_6MHZ } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns sp 2 REG LC_X9_Y7_N1 1 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X9_Y7_N1; Fanout = 1; REG Node = 'sp'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_6MHZ sp } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.099 ns) + CELL(0.918 ns) 7.212 ns ss 3 REG LC_X8_Y4_N8 2 " "Info: 3: + IC(2.099 ns) + CELL(0.918 ns) = 7.212 ns; Loc. = LC_X8_Y4_N8; Fanout = 2; REG Node = 'ss'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.017 ns" { sp ss } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 46.80 % ) " "Info: Total cell delay = 3.375 ns ( 46.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.837 ns ( 53.20 % ) " "Info: Total interconnect delay = 3.837 ns ( 53.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.212 ns" { clk_6MHZ sp ss } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.212 ns" { clk_6MHZ {} clk_6MHZ~combout {} sp {} ss {} } { 0.000ns 0.000ns 1.738ns 2.099ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.090 ns + Longest register pin " "Info: + Longest register to pin delay is 3.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ss 1 REG LC_X8_Y4_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y4_N8; Fanout = 2; REG Node = 'ss'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ss } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(2.322 ns) 3.090 ns SPK 2 PIN PIN_52 0 " "Info: 2: + IC(0.768 ns) + CELL(2.322 ns) = 3.090 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'SPK'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { ss SPK } "NODE_NAME" } } { "spk.vhd" "" { Text "E:/Altera/72/quartus/gequ/spk.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 75.15 % ) " "Info: Total cell delay = 2.322 ns ( 75.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 24.85 % ) " "Info: Total interconnect delay = 0.768 ns ( 24.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { ss SPK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { ss {} SPK {} } { 0.000ns 0.768ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.212 ns" { clk_6MHZ sp ss } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.212 ns" { clk_6MHZ {} clk_6MHZ~combout {} sp {} ss {} } { 0.000ns 0.000ns 1.738ns 2.099ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { ss SPK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { ss {} SPK {} } { 0.000ns 0.768ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 04 19:43:06 2008 " "Info: Processing ended: Sat Oct 04 19:43:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}