gequ.map.rpt

梁祝歌曲

; gequ.vhd                         ; yes             ; User VHDL File                     ; E:/Altera/72/quartus/gequ/gequ.vhd      ;
; clockdiv4.vhd                    ; yes             ; User VHDL File                     ; E:/Altera/72/quartus/gequ/clockdiv4.vhd ;
; spk.vhd                          ; yes             ; User VHDL File                     ; E:/Altera/72/quartus/gequ/spk.vhd       ;
; Block1.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/Altera/72/quartus/gequ/Block1.bdf    ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 144                      ;
;     -- Combinational with no register       ; 74                       ;
;     -- Register only                        ; 18                       ;
;     -- Combinational with a register        ; 52                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 56                       ;
;     -- 3 input functions                    ; 21                       ;
;     -- 2 input functions                    ; 43                       ;
;     -- 1 input functions                    ; 6                        ;
;     -- 0 input functions                    ; 0                        ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 104                      ;
;     -- arithmetic mode                      ; 40                       ;
;     -- qfbk mode                            ; 0                        ;
;     -- register cascade mode                ; 0                        ;
;     -- synchronous clear/load mode          ; 14                       ;
;     -- asynchronous clear/load mode         ; 0                        ;
;                                             ;                          ;
; Total registers                             ; 70                       ;
; Total logic cells in carry chains           ; 43                       ;
; I/O pins                                    ; 2                        ;
; Maximum fan-out node                        ; clockdiv4:inst|clock_int ;
; Maximum fan-out                             ; 28                       ;
; Total fan-out                               ; 496                      ;
; Average fan-out                             ; 3.40                     ;
+---------------------------------------------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name    ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+--------------+
; |Block1                    ; 144 (0)     ; 70           ; 0           ; 0            ; 0       ; 0         ; 0         ; 2    ; 0            ; 74 (0)       ; 18 (0)            ; 52 (0)           ; 43 (0)          ; 0 (0)      ; |Block1                ; work         ;
;    |clockdiv4:inst|        ; 54 (54)     ; 24           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 30 (30)      ; 15 (15)           ; 9 (9)            ; 23 (23)         ; 0 (0)      ; |Block1|clockdiv4:inst ; work         ;
;    |gequ:inst1|            ; 3 (3)       ; 3            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |Block1|gequ:inst1     ; work         ;
;    |spk:inst5|             ; 87 (87)     ; 43           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 44 (44)      ; 3 (3)             ; 40 (40)          ; 20 (20)         ; 0 (0)      ; |Block1|spk:inst5      ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; spk:inst5|HML[3,7,9..11]              ; Stuck at GND due to stuck port data_in ;
; spk:inst5|SPK                         ; Merged with spk:inst5|ss               ;
; Total Number of Removed Registers = 6 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 70    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 14    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Oct 13 20:23:59 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gequ -c gequ
Info: Found 2 design units, including 1 entities, in source file gequ.vhd
    Info: Found design unit 1: gequ-behavioural
    Info: Found entity 1: gequ
Info: Found 2 design units, including 1 entities, in source file clockdiv4.vhd
    Info: Found design unit 1: clockdiv4-behavioural
    Info: Found entity 1: clockdiv4
Info: Found 2 design units, including 1 entities, in source file spk.vhd
    Info: Found design unit 1: SPK-ONE
    Info: Found entity 1: spk
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "spk" for hierarchy "spk:inst5"
Info: Elaborating entity "gequ" for hierarchy "gequ:inst1"
Info: Elaborating entity "clockdiv4" for hierarchy "clockdiv4:inst"
Warning (14130): Reduced register "spk:inst5|HML[11]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "spk:inst5|HML[10]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "spk:inst5|HML[9]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "spk:inst5|HML[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "spk:inst5|HML[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "spk:inst5|SPK" merged to single register "spk:inst5|ss", power-up level changed
Info: Implemented 146 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 144 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 160 megabytes of memory during processing
    Info: Processing ended: Mon Oct 13 20:24:06 2008
    Info: Elapsed time: 00:00:07