gequ.fit.rpt

梁祝歌曲

; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                         ;
+--------------------------------------------------------------------------------+--------------+
; Name                                                                           ; Value        ;
+--------------------------------------------------------------------------------+--------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff           ;
; Mid Wire Use - Fit Attempt 1                                                   ; 7            ;
; Mid Slack - Fit Attempt 1                                                      ; -15523       ;
; Internal Atom Count - Fit Attempt 1                                            ; 136          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 136          ;
; LAB Count - Fit Attempt 1                                                      ; 22           ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.000        ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.864        ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.864        ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:21;1:1     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:20;1:2     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:19;1:3     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:20;1:2     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:19;1:3     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:20;1:2     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:22         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:22         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:19;1:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:4;1:17;2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:4;1:16;2:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:22         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:4;1:18     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:17;1:5     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:7;1:15     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:17;1:5     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:22         ;
; LEs in Chains - Fit Attempt 1                                                  ; 43           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 37           ;
; LABs with Chains - Fit Attempt 1                                               ; 6            ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0            ;
; Time - Fit Attempt 1                                                           ; 0            ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016        ;
+--------------------------------------------------------------------------------+--------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Early Slack - Fit Attempt 1         ; -19075 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 3      ;
; Mid Slack - Fit Attempt 1           ; -15736 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 3      ;
; Late Slack - Fit Attempt 1          ; -15736 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -15356 ;
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Peak Regional Wire - Fit Attempt 1  ; 5      ;
; Mid Slack - Fit Attempt 1           ; -15348 ;
; Late Slack - Fit Attempt 1          ; -15348 ;
; Late Wire Use - Fit Attempt 1       ; 4      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.110  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Oct 13 20:24:09 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off gequ -c gequ
Info: Selected device EPM1270T144C5 for design "gequ"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM570T144A5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144A5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "clockdiv4:inst|clock_int" to use Global clock
    Info: Destination "clockdiv4:inst|clock_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "gequ:inst1|clock_int" to use Global clock
    Info: Destination "gequ:inst1|clock_int" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 4.777 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y7; Fanout = 2; REG Node = 'spk:inst5|ss'
    Info: 2: + IC(2.455 ns) + CELL(2.322 ns) = 4.777 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'spk'
    Info: Total cell delay = 2.322 ns ( 48.61 % )
    Info: Total interconnect delay = 2.455 ns ( 51.39 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources
    Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused P