v3_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V3_1 is
 port(Ina	: in std_logic;
     En  	: in std_logic;
     Outa	: out std_logic);
end V3_1;

architecture a of V3_1 is
		
begin

	Outa <= Ina when En = '0' else
	        'z';
		
end a;