v3_2.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_UNSIGNED.all;
use std.textio.all;

entity V3_2 is
     file Ofile : TEXT open write_mode is "Output_file";
end V3_2;

architecture a of V3_2 is

	component add4
	  port(a		: in std_logic_vector(3 downto 0);
           b		: in std_logic_vector(3 downto 0);
           clk	    : in std_logic;
           dataout 	: out std_logic_vector(3 downto 0));
    end component;
    
	file Ifile1 : TEXT open read_mode is "Input_file";
	signal a		: std_logic_vector(3 downto 0);
    signal b		: std_logic_vector(3 downto 0);
    signal clk	    : std_logic;
    signal dataout : std_logic_vector(3 downto 0);

begin

	dut : add4
	port map(a       => a       ,   
	         b       => b       ,
	         clk     => clk      , 
			 dataout => dataout );		
		
	process(clk)
	
		file Ifile2  : TEXT open read_mode is "Input_file1";
		variable InLine1 : LINE;
		variable InLine2 : LINE;
		variable OutLine : LINE;
		variable InA     : integer;
		variable InB     : integer;
		variable OutD    : integer;
	
	begin	
		if clk = '1' and clk'event then
			readline(Ifile1,InLine1);
			read(InLine1,InA);
			readline(Ifile2,InLine2);
			read(InLine2,InB);
			a <= CONV_STD_LOGIC_VECTOR(InA,10);
			b <= CONV_STD_LOGIC_VECTOR(InB,10);
			dataout <= a + b;
			OutD := CONV_INTEGER(dataout);
			write(OutLine,OutD,right,10);
			writeline(Ofile,OutLine);
		end if;		
	end process;
	
end a;