v15_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity M16x16 is
	port(InA		: in   std_logic_vector(15 downto 0);
	     InB		: in   std_logic_vector(15 downto 0);
	     DOut   	: out  std_logic_vector(31 downto 0);
	     Clk    	: in   std_logic);
end M16x16;

architecture A_M16x16 of M16x16 is
begin
	process
	begin
		wait until Clk = '1' and Clk'event;
			DOut <= InA * InB;
	end process;
end A_M16x16;