time_sim.vhd

台湾全华科技VHDL教材实例

-- Xilinx Vhdl produced by program ngd2vhdl C.18
-- Command: -w M16x16.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Fri Jul 07 22:49:16 2000 
-- Input file: M16x16.nga
-- Output file: time_sim.vhd
-- Tmp file: C:/WINDOWS/TEMP/xil_6
-- Design name: M16x16
-- Xilinx: E:/fndtn
-- # of Entities: 1
-- Device: v50pq240-4

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity M16X16 is 
  port (
    CLK : in STD_LOGIC := 'X'; 
    DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    INA : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    INB : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end M16X16;

architecture STRUCTURE of M16X16 is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal C773_IBUFG : STD_LOGIC; 
  signal CLK_BUFGPED : STD_LOGIC; 
  signal C6_C3_C2_O : STD_LOGIC; 
  signal C6_C5_C2_O : STD_LOGIC; 
  signal C6_C7_C2_O : STD_LOGIC; 
  signal C8_C3_C2_O : STD_LOGIC; 
  signal C8_C5_C2_O : STD_LOGIC; 
  signal C8_C7_C2_O : STD_LOGIC; 
  signal C8_C9_C2_O : STD_LOGIC; 
  signal C8_C11_C2_O : STD_LOGIC; 
  signal C8_C13_C2_O : STD_LOGIC; 
  signal C8_C15_C2_O : STD_LOGIC; 
  signal C8_C17_C2_O : STD_LOGIC; 
  signal C8_C19_C2_O : STD_LOGIC; 
  signal C8_C21_C2_O : STD_LOGIC; 
  signal C8_C23_C2_O : STD_LOGIC; 
  signal C5_C79_O : STD_LOGIC; 
  signal C5_N96 : STD_LOGIC; 
  signal C5_N100 : STD_LOGIC; 
  signal C5_C87_O : STD_LOGIC; 
  signal C5_N104 : STD_LOGIC; 
  signal C5_N108 : STD_LOGIC; 
  signal C5_C95_O : STD_LOGIC; 
  signal C5_N112 : STD_LOGIC; 
  signal C5_N116 : STD_LOGIC; 
  signal C5_C103_O : STD_LOGIC; 
  signal C5_N120 : STD_LOGIC; 
  signal C5_N124 : STD_LOGIC; 
  signal C5_C111_O : STD_LOGIC; 
  signal C5_N128 : STD_LOGIC; 
  signal C5_N132 : STD_LOGIC; 
  signal C5_C119_O : STD_LOGIC; 
  signal C5_N136 : STD_LOGIC; 
  signal C5_N140 : STD_LOGIC; 
  signal C5_C127_O : STD_LOGIC; 
  signal C5_N144 : STD_LOGIC; 
  signal C5_N148 : STD_LOGIC; 
  signal C5_C135_O : STD_LOGIC; 
  signal C5_N152 : STD_LOGIC; 
  signal C5_N156 : STD_LOGIC; 
  signal C5_N160 : STD_LOGIC; 
  signal C5_N94 : STD_LOGIC; 
  signal C5_C204_O : STD_LOGIC; 
  signal C5_N221 : STD_LOGIC; 
  signal C5_N225 : STD_LOGIC; 
  signal C5_C212_O : STD_LOGIC; 
  signal C5_N229 : STD_LOGIC; 
  signal C5_N233 : STD_LOGIC; 
  signal C5_C220_O : STD_LOGIC; 
  signal C5_N237 : STD_LOGIC; 
  signal C5_N241 : STD_LOGIC; 
  signal C5_C228_O : STD_LOGIC; 
  signal C5_N245 : STD_LOGIC; 
  signal C5_N249 : STD_LOGIC; 
  signal C5_C236_O : STD_LOGIC; 
  signal C5_N253 : STD_LOGIC; 
  signal C5_N257 : STD_LOGIC; 
  signal C5_C244_O : STD_LOGIC; 
  signal C5_N261 : STD_LOGIC; 
  signal C5_N265 : STD_LOGIC; 
  signal C5_C252_O : STD_LOGIC; 
  signal C5_N269 : STD_LOGIC; 
  signal C5_N273 : STD_LOGIC; 
  signal C5_C260_O : STD_LOGIC; 
  signal C5_N277 : STD_LOGIC; 
  signal C5_N281 : STD_LOGIC; 
  signal C5_N285 : STD_LOGIC; 
  signal C5_N219 : STD_LOGIC; 
  signal C5_C274_O : STD_LOGIC; 
  signal C5_N291 : STD_LOGIC; 
  signal C5_N295 : STD_LOGIC; 
  signal C5_C282_O : STD_LOGIC; 
  signal C5_N299 : STD_LOGIC; 
  signal C5_N303 : STD_LOGIC; 
  signal C5_C290_O : STD_LOGIC; 
  signal C5_N307 : STD_LOGIC; 
  signal C5_N311 : STD_LOGIC; 
  signal C5_C298_O : STD_LOGIC; 
  signal C5_N315 : STD_LOGIC; 
  signal C5_N319 : STD_LOGIC; 
  signal C5_C306_O : STD_LOGIC; 
  signal C5_N323 : STD_LOGIC; 
  signal C5_N327 : STD_LOGIC; 
  signal C5_C314_O : STD_LOGIC; 
  signal C5_N331 : STD_LOGIC; 
  signal C5_N335 : STD_LOGIC; 
  signal C5_C322_O : STD_LOGIC; 
  signal C5_N339 : STD_LOGIC; 
  signal C5_N343 : STD_LOGIC; 
  signal C5_C330_O : STD_LOGIC; 
  signal C5_N347 : STD_LOGIC; 
  signal C5_N351 : STD_LOGIC; 
  signal C5_N355 : STD_LOGIC; 
  signal C5_N289 : STD_LOGIC; 
  signal C5_C147_O : STD_LOGIC; 
  signal C5_N30 : STD_LOGIC; 
  signal C5_N34 : STD_LOGIC; 
  signal C5_C153_O : STD_LOGIC; 
  signal C5_N38 : STD_LOGIC; 
  signal C5_N42 : STD_LOGIC; 
  signal C5_N171 : STD_LOGIC; 
  signal C5_N174 : STD_LOGIC; 
  signal C5_C159_O : STD_LOGIC; 
  signal C5_N46 : STD_LOGIC; 
  signal C5_N50 : STD_LOGIC; 
  signal C5_N177 : STD_LOGIC; 
  signal C5_N180 : STD_LOGIC; 
  signal C5_C165_O : STD_LOGIC; 
  signal C5_N54 : STD_LOGIC; 
  signal C5_N58 : STD_LOGIC; 
  signal C5_N183 : STD_LOGIC; 
  signal C5_N186 : STD_LOGIC; 
  signal C5_C171_O : STD_LOGIC; 
  signal C5_N62 : STD_LOGIC; 
  signal C5_N66 : STD_LOGIC; 
  signal C5_N189 : STD_LOGIC; 
  signal C5_N192 : STD_LOGIC; 
  signal C5_C177_O : STD_LOGIC; 
  signal C5_N70 : STD_LOGIC; 
  signal C5_N74 : STD_LOGIC; 
  signal C5_N195 : STD_LOGIC; 
  signal C5_N198 : STD_LOGIC; 
  signal C5_C183_O : STD_LOGIC; 
  signal C5_N78 : STD_LOGIC; 
  signal C5_N82 : STD_LOGIC; 
  signal C5_N201 : STD_LOGIC; 
  signal C5_N204 : STD_LOGIC; 
  signal C5_C189_O : STD_LOGIC; 
  signal C5_N86 : STD_LOGIC; 
  signal C5_N90 : STD_LOGIC; 
  signal C5_N207 : STD_LOGIC; 
  signal C5_N210 : STD_LOGIC; 
  signal C5_N213 : STD_LOGIC; 
  signal C5_N216 : STD_LOGIC; 
  signal C5_C397_O : STD_LOGIC; 
  signal C5_C403_O : STD_LOGIC; 
  signal C5_N360 : STD_LOGIC; 
  signal C5_N363 : STD_LOGIC; 
  signal C5_C409_O : STD_LOGIC; 
  signal C5_N366 : STD_LOGIC; 
  signal C5_N369 : STD_LOGIC; 
  signal C5_C415_O : STD_LOGIC; 
  signal C5_N372 : STD_LOGIC; 
  signal C5_N375 : STD_LOGIC; 
  signal C5_C421_O : STD_LOGIC; 
  signal C5_N378 : STD_LOGIC; 
  signal C5_N381 : STD_LOGIC; 
  signal C5_C427_O : STD_LOGIC; 
  signal C5_N384 : STD_LOGIC; 
  signal C5_N387 : STD_LOGIC; 
  signal C5_C433_O : STD_LOGIC; 
  signal C5_N390 : STD_LOGIC; 
  signal C5_N393 : STD_LOGIC; 
  signal C5_C439_O : STD_LOGIC; 
  signal C5_N396 : STD_LOGIC; 
  signal C5_N399 : STD_LOGIC; 
  signal C5_C445_O : STD_LOGIC; 
  signal C5_N402 : STD_LOGIC; 
  signal C5_N405 : STD_LOGIC; 
  signal C5_N408 : STD_LOGIC; 
  signal C5_N411 : STD_LOGIC; 
  signal C5_C342_O : STD_LOGIC; 
  signal C5_C348_O : STD_LOGIC; 
  signal C5_C354_O : STD_LOGIC; 
  signal C5_C360_O : STD_LOGIC; 
  signal C5_C366_O : STD_LOGIC; 
  signal C5_C372_O : STD_LOGIC; 
  signal C5_C378_O : STD_LOGIC; 
  signal C5_C384_O : STD_LOGIC; 
  signal C7_C79_O : STD_LOGIC; 
  signal C7_N97 : STD_LOGIC; 
  signal C7_N101 : STD_LOGIC; 
  signal C7_C87_O : STD_LOGIC; 
  signal C7_N105 : STD_LOGIC; 
  signal C7_N109 : STD_LOGIC; 
  signal C7_C95_O : STD_LOGIC; 
  signal C7_N113 : STD_LOGIC; 
  signal C7_N117 : STD_LOGIC; 
  signal C7_C103_O : STD_LOGIC; 
  signal C7_N121 : STD_LOGIC; 
  signal C7_N125 : STD_LOGIC; 
  signal C7_C111_O : STD_LOGIC; 
  signal C7_N129 : STD_LOGIC; 
  signal C7_N133 : STD_LOGIC; 
  signal C7_C119_O : STD_LOGIC; 
  signal C7_N137 : STD_LOGIC; 
  signal C7_N141 : STD_LOGIC; 
  signal C7_C127_O : STD_LOGIC; 
  signal C7_N145 : STD_LOGIC; 
  signal C7_N149 : STD_LOGIC; 
  signal C7_C135_O : STD_LOGIC; 
  signal C7_N153 : STD_LOGIC; 
  signal C7_N157 : STD_LOGIC; 
  signal C7_N161 : STD_LOGIC; 
  signal C7_N95 : STD_LOGIC; 
  signal C7_C204_O : STD_LOGIC; 
  signal C7_N222 : STD_LOGIC; 
  signal C7_N226 : STD_LOGIC; 
  signal C7_C212_O : STD_LOGIC; 
  signal C7_N230 : STD_LOGIC; 
  signal C7_N234 : STD_LOGIC; 
  signal C7_C220_O : STD_LOGIC; 
  signal C7_N238 : STD_LOGIC; 
  signal C7_N242 : STD_LOGIC; 
  signal C7_C228_O : STD_LOGIC; 
  signal C7_N246 : STD_LOGIC; 
  signal C7_N250 : STD_LOGIC; 
  signal C7_C236_O : STD_LOGIC; 
  signal C7_N254 : STD_LOGIC; 
  signal C7_N258 : STD_LOGIC; 
  signal C7_C244_O : STD_LOGIC; 
  signal C7_N262 : STD_LOGIC; 
  signal C7_N266 : STD_LOGIC; 
  signal C7_C252_O : STD_LOGIC; 
  signal C7_N270 : STD_LOGIC; 
  signal C7_N274 : STD_LOGIC; 
  signal C7_C260_O : STD_LOGIC; 
  signal C7_N278 : STD_LOGIC; 
  signal C7_N282 : STD_LOGIC; 
  signal C7_N286 : STD_LOGIC; 
  signal C7_N220 : STD_LOGIC; 
  signal C7_C274_O : STD_LOGIC; 
  signal C7_N292 : STD_LOGIC; 
  signal C7_N296 : STD_LOGIC; 
  signal C7_C282_O : STD_LOGIC; 
  signal C7_N300 : STD_LOGIC; 
  signal C7_N304 : STD_LOGIC; 
  signal C7_C290_O : STD_LOGIC; 
  signal C7_N308 : STD_LOGIC; 
  signal C7_N312 : STD_LOGIC; 
  signal C7_C298_O : STD_LOGIC; 
  signal C7_N316 : STD_LOGIC; 
  signal C7_N320 : STD_LOGIC; 
  signal C7_C306_O : STD_LOGIC; 
  signal C7_N324 : STD_LOGIC; 
  signal C7_N328 : STD_LOGIC; 
  signal C7_C314_O : STD_LOGIC; 
  signal C7_N332 : STD_LOGIC; 
  signal C7_N336 : STD_LOGIC; 
  signal C7_C322_O : STD_LOGIC; 
  signal C7_N340 : STD_LOGIC; 
  signal C7_N344 : STD_LOGIC; 
  signal C7_C330_O : STD_LOGIC; 
  signal C7_N348 : STD_LOGIC; 
  signal C7_N352 : STD_LOGIC; 
  signal C7_N356 : STD_LOGIC; 
  signal C7_N290 : STD_LOGIC; 
  signal C7_C147_O : STD_LOGIC; 
  signal C7_N31 : STD_LOGIC; 
  signal C7_N35 : STD_LOGIC; 
  signal C7_C153_O : STD_LOGIC; 
  signal C7_N39 : STD_LOGIC; 
  signal C7_N43 : STD_LOGIC; 
  signal C7_N172 : STD_LOGIC; 
  signal C7_N175 : STD_LOGIC; 
  signal C7_C159_O : STD_LOGIC; 
  signal C7_N47 : STD_LOGIC; 
  signal C7_N51 : STD_LOGIC; 
  signal C7_N178 : STD_LOGIC; 
  signal C7_N181 : STD_LOGIC; 
  signal C7_C165_O : STD_LOGIC; 
  signal C7_N55 : STD_LOGIC; 
  signal C7_N59 : STD_LOGIC; 
  signal C7_N184 : STD_LOGIC; 
  signal C7_N187 : STD_LOGIC; 
  signal C7_C171_O : STD_LOGIC; 
  signal C7_N63 : STD_LOGIC; 
  signal C7_N67 : STD_LOGIC; 
  signal C7_N190 : STD_LOGIC; 
  signal C7_N193 : STD_LOGIC; 
  signal C7_C177_O : STD_LOGIC; 
  signal C7_N71 : STD_LOGIC; 
  signal C7_N75 : STD_LOGIC; 
  signal C7_N196 : STD_LOGIC; 
  signal C7_N199 : STD_LOGIC; 
  signal C7_C183_O : STD_LOGIC; 
  signal C7_N79 : STD_LOGIC; 
  signal C7_N83 : STD_LOGIC; 
  signal C7_N202 : STD_LOGIC; 
  signal C7_N205 : STD_LOGIC; 
  signal C7_C189_O : STD_LOGIC; 
  signal C7_N87 : STD_LOGIC; 
  signal C7_N91 : STD_LOGIC; 
  signal C7_N208 : STD_LOGIC; 
  signal C7_N211 : STD_LOGIC; 
  signal C7_N214 : STD_LOGIC; 
  signal C7_N217 : STD_LOGIC; 
  signal C7_C394_O : STD_LOGIC; 
  signal C7_N413 : STD_LOGIC; 
  signal C7_N416 : STD_LOGIC; 
  signal C7_C400_O : STD_LOGIC; 
  signal C7_N361 : STD_LOGIC; 
  signal C7_N364 : STD_LOGIC; 
  signal C7_N419 : STD_LOGIC; 
  signal C7_N422 : STD_LOGIC; 
  signal C7_C406_O : STD_LOGIC; 
  signal C7_N367 : STD_LOGIC; 
  signal C7_N370 : STD_LOGIC; 
  signal C7_N425 : STD_LOGIC; 
  signal C7_N428 : STD_LOGIC; 
  signal C7_C412_O : STD_LOGIC; 
  signal C7_N373 : STD_LOGIC; 
  signal C7_N376 : STD_LOGIC; 
  signal C7_N431 : STD_LOGIC; 
  signal C7_N434 : STD_LOGIC; 
  signal C7_C418_O : STD_LOGIC;