v4_11.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_11 is 
	 port(a,b,c	 : in  std_logic_vector(2 downto 0);
	      o0     : out std_logic_vector(8 downto 0);
	      o1     : out std_logic_vector(8 downto 0));
end V4_11;

architecture A of V4_11 is
begin
	process(a,b,c)
	begin
		o0 <= a & b * c;
		o1 <= (a & b) * c;
	end process;
end A;