v4_10.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity V4_10 is
port(a_std			: in  std_logic_vector(7 downto 0);
     b_std   	    : in  std_logic_vector(7 downto 0);
     a_int          : in  integer;
     b_int          : in  integer;
     a_real         : in  real;
     std_abs 	    : out std_logic_vector(7 downto 0);
     int_exp        : out integer;
     out_real       : out real);
end V4_10;

architecture a of V4_10 is
	
begin
                  
	std_abs <= abs(a_std);
	int_exp <= a_int ** b_int;	
	out_real <= a_real ** a_int;           
    
end a;