v4_9.vhd

台湾全华科技VHDL教材实例

library ieee;
--use ieee.NUMERIC_BIT.all;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;

entity V4_9 is
 port(a_std			: in  std_logic_vector(7 downto 0);
      b_std   	    : in  std_logic_vector(7 downto 0);
      a_bit         : in  bit_vector(7 downto 0);
      b_bit         : in  bit_vector(7 downto 0);
      a_int         : in  integer;
      b_int         : in  integer;
      std_out 	    : out std_logic_vector(7 downto 0);
      bit_out       : out bit_vector(7 downto 0);
      int_out       : out integer);
end V4_9;

architecture a of V4_9 is
	
begin
                  
	std_out <= std_logic_vector(unsigned (a_std) / unsigned (b_std));
    --bit_out <= bit_vector(unsigned (a_bit) / unsigned (b_bit));
	int_out <= a_int / b_int;             
    
end a;