v4_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_3 is
 port(aIn		  : in  bit_vector(7 downto 0);
      sllout	  : out bit_vector(7 downto 0);
      srlout	  : out bit_vector(7 downto 0);
      slaout	  : out bit_vector(7 downto 0);
      sraout	  : out bit_vector(7 downto 0);
      rolout	  : out bit_vector(7 downto 0);
      rorout	  : out bit_vector(7 downto 0);
      sht         : in  integer);
end V4_3;

architecture a of V4_3 is
	
begin
    
    sllout <= aIn sll sht;
    srlout <= aIn srl sht;
    slaout <= aIn sla sht;
    sraout <= aIn sra sht;
    rolout <= aIn rol sht;
    rorout <= aIn ror sht; 
    
end a;