v4_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_0 is
port(a_std		   : in std_logic;
     b_std   	   : in std_logic;
     a_bit         : in bit;
     b_bit         : in bit;
     std_out 	   : out std_logic;
     bit_out       : out bit);
end V4_0;

architecture a of V4_0 is
	
begin
    
    bit_out <= a_bit and b_bit;              
	std_out <= a_std and b_std;             
    
end a;