v4_6.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

entity V4_6 is
 port(aIn			: in  std_logic_vector(7 downto 0);
      sllout	    : out std_logic_vector(7 downto 0);
      srlout	    : out std_logic_vector(7 downto 0);
      slsout	    : out std_logic_vector(7 downto 0);
      srsout	    : out std_logic_vector(7 downto 0);
      Sht           : in  std_logic_vector(2 downto 0));
end V4_6;

architecture a of V4_6 is
	
begin
    
    sllout <= std_logic_vector(unsigned(shl(unsigned(aIn),unsigned(Sht))));
    srlout <= std_logic_vector(unsigned (shr(unsigned (aIn), unsigned (Sht))));
    slsout <= std_logic_vector(signed(shl(signed (aIn), unsigned (Sht))));
    srsout <= std_logic_vector(signed (shr(signed (aIn), unsigned (Sht))));
    
end a;