v4_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_1 is
  port(aIn		: in std_logic_vector(3 downto 0);
       dout 	: out std_logic_vector(1 downto 0));
end V4_1;

architecture a of V4_1 is
	
begin
    
    process(aIn)
    begin
    	if aIn > "1000" then
    		dout <= "00";
    	elsif aIn > 6 then
    		dout <= "01";
    	elsif 4 > aIn then
    	 	dout <= "11";
    	else
    		dout <= "10";
    	end if;
    end process;          
    
end a;