v4_7.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V4_7 is
	port(a_std			: in  std_logic_vector(7 downto 0);
         b_std   	    : in  std_logic_vector(7 downto 0);
         a_bit          : in  bit_vector(7 downto 0);
         b_bit          : in  bit_vector(7 downto 0);
         a_int          : in  integer;
         b_int          : in  integer;
         std_out 	    : out std_logic_vector(7 downto 0);
         bit_out        : out bit_vector(7 downto 0);
         int_out        : out integer);
end V4_7;

architecture a of V4_7 is
	
begin
    
	bit_out <= a_bit + b_bit;              
	std_out <= a_std + b_std;
	int_out <= a_int + b_int;             
    
end a;