v4_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_4 is
 port(aIn	     : in  std_logic_vector(7 downto 0);
      sllout	 : out std_logic_vector(7 downto 0);
      srlout	 : out std_logic_vector(7 downto 0);
      sht        : in  std_logic_vector(2 downto 0));
end V4_4;

architecture a of V4_4 is
	
begin
    
    sllout <= SHL(aIn,sht);
    srlout <= SHR(aIn,sht);
    
end a;