v4_8.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_8 is
 port(a_std		: in  std_logic_vector(7 downto 0);
      b_std   	: in  std_logic_vector(7 downto 0);
      std_out 	: out std_logic_vector(8 downto 0));
end V4_8;

architecture a of V4_8 is
	
begin
    
    std_out <= a_std(7) & a_std + b_std(7) & b_std;          
    
end a;