v4_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity V4_5 is
 port(aIn	     : in  std_logic_vector(7 downto 0);
      slsout	 : out std_logic_vector(7 downto 0);
      srsout	 : out std_logic_vector(7 downto 0);
      sht        : in  std_logic_vector(2 downto 0));
end V4_5;

architecture a of V4_5 is
	
begin
    
    slsout <= SHL(aIn,sht);
    srsout <= SHR(aIn,sht);
    
end a;