v4_71.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 27 行

library ieee;
use ieee.NUMERIC_BIT.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V4_71 is
 port(a_std			: in  std_logic_vector(7 downto 0);
      b_std   	    : in  std_logic_vector(7 downto 0);
      a_bit         : in  bit_vector(7 downto 0);
      b_bit         : in  bit_vector(7 downto 0);
      a_int         : in  integer;
      b_int         : in  integer;
      std_out 	    : out std_logic_vector(7 downto 0);
      bit_out       : out bit_vector(7 downto 0);
      int_out       : out integer);
end V4_71;

architecture a of V4_71 is
	
begin
    
    bit_out <= bit_vector(unsigned(a_bit) + unsigned (b_bit));              
	std_out <= a_std + b_std;
	int_out <= a_int + b_int;             
    
end a;