time_sim.vhd

台湾全华科技VHDL教材实例

  SYN596_FGBLOCK_LUTRAM_FLUT_AND1_43 : X_AND2 
    port map (
      I0 => SYN596_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(3, 0),
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN596_FGBLOCK_LUTRAM_FLUT_AND2_44 : X_AND2 
    port map (
      I0 => SYN596_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN596_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN596_FGBLOCK_LUTRAM_FLUT_AND3_45 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 1),
      I1 => SYN596_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN596_FGBLOCK_LUTRAM_FLUT_AND4_46 : X_AND2 
    port map (
      I0 => SYN596_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(3, 1),
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN596_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN596_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN596_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN596_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN607_DFF_OUT_YMUX : X_BUF 
    port map (
      I => SYN607_H,
      O => SYN607
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND0_47 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 2),
      I1 => SYN607_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND1_48 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(1, 2),
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND2_49 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN607_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND3_50 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 3),
      I1 => SYN607_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND4_51 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(1, 3),
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN607_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN607_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN607_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN607_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND0_52 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 0),
      I1 => SYN607_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND0
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND1_53 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_GLUT_AND1_0_INV,
      I1 => LARRAY(0, 0),
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND1
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND2_54 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_GLUT_AND2_0_INV,
      I1 => SYN607_FGBLOCK_LUTRAM_GLUT_AND2_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND2
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND3_55 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 1),
      I1 => SYN607_FGBLOCK_LUTRAM_GLUT_AND3_1_INV,
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND3
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND4_56 : X_AND2 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_GLUT_AND4_0_INV,
      I1 => LARRAY(0, 1),
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND4
    );
  SYN607_FGBLOCK_LUTRAM_GLUT_AND5 : X_AND3 
    port map (
      I0 => SYN607_FGBLOCK_LUTRAM_GLUT_AND2,
      I1 => SYN607_FGBLOCK_LUTRAM_GLUT_AND5_1_INV,
      I2 => SYN607_FGBLOCK_LUTRAM_GLUT_AND5_2_INV,
      O => SYN607_FGBLOCK_LUTRAM_GLUT_AND5_3_INV
    );
  SYN607_HLUT_AND0 : X_AND2 
    port map (
      I0 => SYN607_HLUT_AND0_0_INV,
      I1 => SYN607_HLUT_AND0_1_INV,
      O => SYN607_HLUT_AND0_2_INV
    );
  C3_N32_DFF_OUT_XMUX : X_BUF 
    port map (
      I => C3_N32_F,
      O => C3_N32
    );
  C3_N32_FGBLOCK_LUTRAM_FLUT_AND0_57 : X_AND2 
    port map (
      I0 => C3_N32_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => N7,
      O => C3_N32_FGBLOCK_LUTRAM_FLUT_AND0
    );
  C3_N32_FGBLOCK_LUTRAM_FLUT_AND1_58 : X_AND2 
    port map (
      I0 => C3_N32_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => C3_N32_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      O => C3_N32_FGBLOCK_LUTRAM_FLUT_AND1
    );
  C3_N32_FGBLOCK_LUTRAM_FLUT_AND2 : X_AND2 
    port map (
      I0 => C3_N32_FGBLOCK_LUTRAM_FLUT_AND1,
      I1 => C3_N32_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => C3_N32_FGBLOCK_LUTRAM_FLUT_AND2_2_INV
    );
  SYN358_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN358_F,
      O => SYN358
    );
  SYN358_FGBLOCK_LUTRAM_FLUT_AND0_59 : X_AND2 
    port map (
      I0 => PRESENTSTATE(2),
      I1 => INPUTCNT(1),
      O => SYN358_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN358_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND3 
    port map (
      I0 => SYN358_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => SYN358_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      I2 => INPUTCNT(0),
      O => SYN358_F
    );
  SYN356_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN356_F,
      O => SYN356
    );
  SYN356_FGBLOCK_LUTRAM_FLUT_AND0_60 : X_AND2 
    port map (
      I0 => PRESENTSTATE(0),
      I1 => SYN356_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN356_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN356_FGBLOCK_LUTRAM_FLUT_AND1_61 : X_AND2 
    port map (
      I0 => PRESENTSTATE(0),
      I1 => SYN356_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      O => SYN356_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN356_FGBLOCK_LUTRAM_FLUT_AND2 : X_AND2 
    port map (
      I0 => SYN356_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN356_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN356_FGBLOCK_LUTRAM_FLUT_AND2_2_INV
    );
  CLK_CLKINMUX : X_BUF 
    port map (
      I => CLK,
      O => CLK_INT
    );
  DENTER_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => DENTER,
      O => DENTER_INBLOCK_I
    );
  DENTER_INBLOCK_I2MUX : X_BUF 
    port map (
      I => DENTER_INBLOCK_I,
      O => N_DENTER
    );
  IND_0_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => IND(0),
      O => IND_0_INBLOCK_I
    );
  IND_0_INBLOCK_I1MUX : X_BUF 
    port map (
      I => IND_0_INBLOCK_I,
      O => N_IND(0)
    );
  IND_1_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => IND(1),
      O => IND_1_INBLOCK_I
    );
  IND_1_INBLOCK_I2MUX : X_BUF 
    port map (
      I => IND_1_INBLOCK_I,
      O => N_IND(1)
    );
  IND_2_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => IND(2),
      O => IND_2_INBLOCK_I
    );
  IND_2_INBLOCK_I2MUX : X_BUF 
    port map (
      I => IND_2_INBLOCK_I,
      O => N_IND(2)
    );
  IND_3_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => IND(3),
      O => IND_3_INBLOCK_I
    );
  IND_3_INBLOCK_I2MUX : X_BUF 
    port map (
      I => IND_3_INBLOCK_I,
      O => N_IND(3)
    );
  INDATA_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => INDATA,
      O => INDATA_INBLOCK_I
    );
  INDATA_INBLOCK_I2MUX : X_BUF 
    port map (
      I => INDATA_INBLOCK_I,
      O => N_INDATA
    );
  INPINN_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => INPINN,
      O => INPINN_INBLOCK_I
    );
  INPINN_INBLOCK_I2MUX : X_BUF 
    port map (
      I => INPINN_INBLOCK_I,
      O => N_INPINN
    );
  INPUTCNT_0_SR_62 : X_BUF 
    port map (
      I => N782,
      O => INPUTCNT_0_SR
    );
  INPUTCNT_0_DFF_OUT_DFFY : X_FF 
    port map (
      I => INPUTCNT_0_F,
      CLK => CLK_BUFGED,
      CE => N51,
      SET => GND,
      RST => INPUTCNT_0_DFF_OUT_DFFY_GSR_OR,
      O => INPUTCNT_0_DFF_OUT_QYDFF
    );
  INPUTCNT_0_DFF_OUT_DFFX : X_FF 
    port map (
      I => INPUTCNT_0_G,
      CLK => CLK_BUFGED,
      CE => N51,
      SET => GND,
      RST => INPUTCNT_0_DFF_OUT_DFFX_GSR_OR,
      O => INPUTCNT_0_DFF_OUT_QXDFF
    );
  INPUTCNT_0_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => INPUTCNT_0_DFF_OUT_QXDFF,
      O => INPUTCNT(1)
    );
  INPUTCNT_0_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => INPUTCNT_0_DFF_OUT_QYDFF,
      O => INPUTCNT(0)
    );
  INPUTCNT_0_DFF_OUT_DFFY_GSR_OR_63 : X_OR2 
    port map (
      I0 => INPUTCNT_0_SR,
      I1 => GSR,
      O => INPUTCNT_0_DFF_OUT_DFFY_GSR_OR
    );
  INPUTCNT_0_DFF_OUT_DFFX_GSR_OR_64 : X_OR2 
    port map (
      I0 => INPUTCNT_0_SR,
      I1 => GSR,
      O => INPUTCNT_0_DFF_OUT_DFFX_GSR_OR
    );
  INPUTCNT_0_FGBLOCK_LUTRAM_FLUT_OBUF : X_INV 
    port map (
      I => INPUTCNT(0),
      O => INPUTCNT_0_F
    );
  INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND0_65 : X_AND2 
    port map (
      I0 => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => INPUTCNT(1),
      O => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND0
    );
  INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND1_66 : X_AND2 
    port map (
      I0 => INPUTCNT(0),
      I1 => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND1
    );
  INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2 : X_AND2 
    port map (
      I0 => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV,
      I1 => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_1_INV,
      O => INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_2_I