time_sim.vhd

台湾全华科技VHDL教材实例

    );
  N49_HLUT_AND0 : X_AND2 
    port map (
      I0 => N49_HLUT_AND0_0_INV,
      I1 => N49_F,
      O => N49_H
    );
  N51_SR_8 : X_BUF 
    port map (
      I => N782,
      O => N51_SR
    );
  N51_H1_9 : X_BUF 
    port map (
      I => N_RESET,
      O => N51_H1
    );
  N51_DFF_OUT_DFFY : X_FF 
    port map (
      I => N51_G,
      CLK => CLK_BUFGED,
      CE => N51,
      SET => GND,
      RST => N51_DFF_OUT_DFFY_GSR_OR,
      O => N51_DFF_OUT_QYDFF
    );
  N51_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N51_H,
      O => C11_N80
    );
  N51_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => N51_DFF_OUT_QYDFF,
      O => INPUTCNT(2)
    );
  N51_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N51_F,
      O => N51
    );
  N51_DFF_OUT_DFFY_GSR_OR_10 : X_OR2 
    port map (
      I0 => N51_SR,
      I1 => GSR,
      O => N51_DFF_OUT_DFFY_GSR_OR
    );
  N51_FGBLOCK_LUTRAM_FLUT_AND0_11 : X_AND2 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => PRESENTSTATE(2),
      O => N51_FGBLOCK_LUTRAM_FLUT_AND0
    );
  N51_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND3 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => N51_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      I2 => N51_FGBLOCK_LUTRAM_FLUT_AND1_2_INV,
      O => N51_F
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND0_12 : X_AND2 
    port map (
      I0 => INPUTCNT(1),
      I1 => N51_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => N51_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND1_13 : X_AND2 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => INPUTCNT(0),
      O => N51_FGBLOCK_LUTRAM_GLUT_AND1
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND2_14 : X_AND2 
    port map (
      I0 => INPUTCNT(2),
      I1 => N51_FGBLOCK_LUTRAM_GLUT_AND2_1_INV,
      O => N51_FGBLOCK_LUTRAM_GLUT_AND2
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND3_15 : X_AND2 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_GLUT_AND3_0_INV,
      I1 => N51_FGBLOCK_LUTRAM_GLUT_AND3_1_INV,
      O => N51_FGBLOCK_LUTRAM_GLUT_AND3
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND4_16 : X_AND2 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_GLUT_AND4_0_INV,
      I1 => INPUTCNT(2),
      O => N51_FGBLOCK_LUTRAM_GLUT_AND4
    );
  N51_FGBLOCK_LUTRAM_GLUT_AND5 : X_AND2 
    port map (
      I0 => N51_FGBLOCK_LUTRAM_GLUT_AND3,
      I1 => N51_FGBLOCK_LUTRAM_GLUT_AND5_1_INV,
      O => N51_FGBLOCK_LUTRAM_GLUT_AND5_2_INV
    );
  N51_HLUT_AND0 : X_AND2 
    port map (
      I0 => N51_H1,
      I1 => N51_F,
      O => N51_H
    );
  SYN603_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN603_F,
      O => SYN603
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND0_17 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 2),
      I1 => SYN603_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND1_18 : X_AND2 
    port map (
      I0 => SYN603_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(0, 2),
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND2_19 : X_AND2 
    port map (
      I0 => SYN603_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN603_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND3_20 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 3),
      I1 => SYN603_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND4_21 : X_AND2 
    port map (
      I0 => SYN603_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(0, 3),
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN603_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN603_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN603_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN603_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN603_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN600_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN600_F,
      O => SYN600
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND0_22 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 0),
      I1 => SYN600_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND1_23 : X_AND2 
    port map (
      I0 => SYN600_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(1, 0),
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND2_24 : X_AND2 
    port map (
      I0 => SYN600_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN600_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND3_25 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 1),
      I1 => SYN600_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND4_26 : X_AND2 
    port map (
      I0 => SYN600_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(1, 1),
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN600_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN600_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN600_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN600_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN600_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN599_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN599_F,
      O => SYN599
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND0_27 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 2),
      I1 => SYN599_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND1_28 : X_AND2 
    port map (
      I0 => SYN599_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(2, 2),
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND2_29 : X_AND2 
    port map (
      I0 => SYN599_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN599_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND3_30 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 3),
      I1 => SYN599_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND4_31 : X_AND2 
    port map (
      I0 => SYN599_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(2, 3),
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN599_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN599_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN599_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN599_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN599_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN598_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN598_F,
      O => SYN598
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND0_32 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 0),
      I1 => SYN598_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND1_33 : X_AND2 
    port map (
      I0 => SYN598_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(2, 0),
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND2_34 : X_AND2 
    port map (
      I0 => SYN598_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN598_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND3_35 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 1),
      I1 => SYN598_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND4_36 : X_AND2 
    port map (
      I0 => SYN598_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(2, 1),
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN598_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN598_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN598_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN598_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN598_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN597_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN597_F,
      O => SYN597
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND0_37 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 2),
      I1 => SYN597_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND1_38 : X_AND2 
    port map (
      I0 => SYN597_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(3, 2),
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND2_39 : X_AND2 
    port map (
      I0 => SYN597_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN597_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND3_40 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 3),
      I1 => SYN597_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND4_41 : X_AND2 
    port map (
      I0 => SYN597_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(3, 3),
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN597_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN597_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN597_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN597_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN597_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN596_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN596_F,
      O => SYN596
    );
  SYN596_FGBLOCK_LUTRAM_FLUT_AND0_42 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 0),
      I1 => SYN596_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN596_FGBLOCK_LUTRAM_FLUT_AND0
    );