time_sim.vhd

台湾全华科技VHDL教材实例

  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND4_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal NMATCH_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal N_NMATCH_DFF_OUT_LATCHY_LATCH_1_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_FLUT_AND1_3_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_GLUT_AND1_2_INV : STD_LOGIC; 
  signal N_NMATCH_FGBLOCK_LUTRAM_GLUT_AND1_3_INV : STD_LOGIC; 
  signal N_NMATCH_HLUT_AND0_0_INV : STD_LOGIC; 
  signal N_NMATCH_HLUT_AND0_1_INV : STD_LOGIC; 
  signal N_NMATCH_HLUT_AND1_1_INV : STD_LOGIC; 
  signal N_NMATCH_HLUT_AND1_2_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal PRESENTSTATE_1_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal PINCNT : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal INPUTCNT : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal PRESENTSTATE : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal N_IND : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal LARRAY : STD_LOGIC_VECTOR2 ( 3 downto 0 , 3 downto 0 ); 
  signal INPUTDIGIT : STD_LOGIC_VECTOR2 ( 3 downto 0 , 3 downto 0 ); 
begin
  C398 : X_CKBUF 
    port map (
      I => CLK_INT,
      O => CLK_BUFGED
    );
  C399 : X_CKBUF 
    port map (
      I => N208,
      O => N208_BUFGED
    );
  N782_SR_0 : X_BUF 
    port map (
      I => N204,
      O => N782_SR
    );
  N782_DIN_1 : X_BUF 
    port map (
      I => PRESENTSTATE(2),
      O => N782_DIN
    );
  N782_DFF_OUT_DFFY : X_FF 
    port map (
      I => N782_DIN,
      CLK => CLK_BUFGED,
      CE => C3_N32,
      SET => GND,
      RST => N782_DFF_OUT_DFFY_GSR_OR,
      O => N782_DFF_OUT_QYDFF
    );
  N782_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N782_G,
      O => N208
    );
  N782_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => N782_DFF_OUT_QYDFF,
      O => PRESENTSTATE(3)
    );
  N782_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N782_F,
      O => N782
    );
  N782_DFF_OUT_DFFY_GSR_OR_2 : X_OR2 
    port map (
      I0 => N782_SR,
      I1 => GSR,
      O => N782_DFF_OUT_DFFY_GSR_OR
    );
  N782_FGBLOCK_LUTRAM_FLUT_AND0 : X_AND2 
    port map (
      I0 => N782_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => N_RESET,
      O => N782_FGBLOCK_LUTRAM_FLUT_AND0_2_INV
    );
  N782_FGBLOCK_LUTRAM_GLUT_AND0_3 : X_AND2 
    port map (
      I0 => N782_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => N_RESET,
      O => N782_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N782_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND2 
    port map (
      I0 => N782_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => N782_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => N782_G
    );
  C10_N80_DFF_OUT_YMUX : X_INV 
    port map (
      I => N_RESET,
      O => N204
    );
  C10_N80_DFF_OUT_XMUX : X_BUF 
    port map (
      I => C10_N80_F,
      O => C10_N80
    );
  C10_N80_FGBLOCK_LUTRAM_FLUT_AND0 : X_AND2 
    port map (
      I0 => N_RESET,
      I1 => N49,
      O => C10_N80_F
    );
  N49_SR_4 : X_BUF 
    port map (
      I => N204,
      O => N49_SR
    );
  N49_H1_5 : X_BUF 
    port map (
      I => PRESENTSTATE(0),
      O => N49_H1
    );
  N49_DFF_OUT_DFFY : X_FF 
    port map (
      I => N49_G,
      CLK => CLK_BUFGED,
      CE => C3_N32,
      SET => N49_DFF_OUT_DFFY_GSR_OR,
      RST => GND,
      O => N49_DFF_OUT_QYDFF
    );
  N49_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N49_G,
      O => N7
    );
  N49_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => N49_DFF_OUT_QYDFF,
      O => PRESENTSTATE(0)
    );
  N49_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N49_H,
      O => N49
    );
  N49_DFF_OUT_DFFY_GSR_OR_6 : X_OR2 
    port map (
      I0 => N49_SR,
      I1 => GSR,
      O => N49_DFF_OUT_DFFY_GSR_OR
    );
  N49_FGBLOCK_LUTRAM_FLUT_AND0_7 : X_AND2 
    port map (
      I0 => N49_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => N49_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => N49_FGBLOCK_LUTRAM_FLUT_AND0
    );
  N49_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND3 
    port map (
      I0 => N49_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => PRESENTSTATE(1),
      I2 => N49_FGBLOCK_LUTRAM_FLUT_AND1_2_INV,
      O => N49_F
    );
  N49_FGBLOCK_LUTRAM_GLUT_AND0 : X_AND2 
    port map (
      I0 => N49_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => N49_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => N49_FGBLOCK_LUTRAM_GLUT_AND0_2_INV