v10_0.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(D  : in  std_logic;
         Q  : out std_logic;
         Clk : in std_logic);
end DFF;

architecture A_DFF of DFF is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            Q <= D;
        end if;
    end process;
end A_DFF;