v10_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity TBus is
    port(DataB  : inout  std_logic_vector(7 downto 0);
         DIn    : in     std_logic_vector(7 downto 0);
         DOut   : out    std_logic_vector(7 downto 0);
         Rd     : in     std_logic;
         CE     : in     std_logic);
end TBus;

architecture A_TBus of TBus is
    
begin
    DataB <= DIn when CE = '0' and Rd = '0' else
             (others => 'Z');
    DOut <= DataB when CE = '0' and Rd = '1' else
            (others => '1');
end A_TBus;