v10_2.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity DFF is
    port(D1  : in   bit;
         D2  : in   bit;
         Q   : out  bit;
         Clk : in   bit);
end DFF;

architecture A_DFF of DFF is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then    
            Q <= D1;
        end if;
    end process;
    Q <= D2;
    
end A_DFF;