v10_7.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use std.textio.all;

entity tb is
end tb;

architecture a_tb of tb is

    component Add4In
    port(D1  : in  std_logic_vector(7 downto 0);
         D2  : in  std_logic_vector(7 downto 0);
         D3  : in  std_logic_vector(7 downto 0);
         D4  : in  std_logic_vector(7 downto 0);
         Q   : out std_logic_vector(9 downto 0);
         Clk : in  std_logic);
    end component;
    
    signal D1   : std_logic_vector(7 downto 0) := (others => '1');
    signal D2   : std_logic_vector(7 downto 0) := (others => '1');
    signal D3   : std_logic_vector(7 downto 0) := (others => '0');
    signal D4   : std_logic_vector(7 downto 0) := (others => '0');
    signal Q    : std_logic_vector(9 downto 0);
    signal Clk  : std_logic := '0';                  

begin

    dut : Add4In
    port map(D1    => D1    ,
             D2    => D2    ,
             D3    => D3    ,
             D4    => D4    ,
             Q     => Q     ,
             Clk   => Clk   );
    
    Clk <= not Clk after 20 ns;
    
    process
        file InputD : text open read_mode is "TestData.dat";
        variable DLine : LINE;
        variable Data1 : integer;
        variable Data2 : integer;
        variable Data3 : integer;
        variable Data4 : integer;
    begin
        wait until Clk = '1' and Clk'event;
        	readline(InputD,DLine);
        	read(DLine,Data1);
        	read(DLine,Data2);
        	read(DLine,Data3);
        	read(DLine,Data4);
            D1 <= CONV_STD_LOGIC_VECTOR(Data1,8);
            D2 <= CONV_STD_LOGIC_VECTOR(Data2,8);
            D3 <= CONV_STD_LOGIC_VECTOR(Data3,8);
            D4 <= CONV_STD_LOGIC_VECTOR(Data4,8);
    end process;
    
end a_tb;