v10_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Add is
    port(D1  : in  std_logic_vector(7 downto 0);
         D2  : in  std_logic_vector(7 downto 0);
         DO  : out std_logic_vector(7 downto 0);
         CE  : in  std_logic;
         Clk : in  std_logic);
end Add;

architecture A_Add of Add is
    
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            if CE = '0' then
                DO <= D1 + D2;
            else
                DO <= (others => '0');
            end if;
        end if;
    end process;
end A_Add;