v10_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(D  : in  std_logic;
         Q  : out std_logic;
         Rst : in std_logic;
         Clk : in std_logic);
end DFF;

architecture A_DFF of DFF is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
        	if Rst = '0' then
        		Q <= '0';
        	else
            	Q <= D after 5 ns;
            end if;
        end if;
    end process;
end A_DFF;  

library ieee;
use ieee.std_logic_1164.all;

entity top is  
    port(D  : in  std_logic;
         Q  : out std_logic;
         OE : in std_logic;
         Rst : in std_logic;
         Clk : in std_logic);
end top;

architecture A_top of top is

	component DFF
    port(D   : in  std_logic;
         Q   : out std_logic;
         Rst : in  std_logic;
         OE  : in  std_logic;
         Clk : in  std_logic);
	end component; 
		                 
begin

	SRDFF : DFF
	port map(D    => D   ,
	       	 Q    => Q   ,
	         Rst  => Rst ,
	         OE   => OE  ,
	         Clk  => Clk );

end A_top;