v5_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V5_3 is
port(sel     : in std_logic_vector(1 downto 0);
     a       : in  std_logic;
     b       : in  std_logic;
     c       : in  std_logic;
     d       : in  std_logic;
     Dataout : out std_logic);
end V5_3;

architecture a of V5_3 is
	
begin
    
    process (sel)
	begin
		case sel is
			when "00" =>
				Dataout <= a;
			when "01" =>
				Dataout <= b;
			when "10" =>
				Dataout <= c;
			when "11" =>
				Dataout <= d;
			when others =>
				Dataout <= a;
			end case;
	end process;    	 
    
end a;