v5_6.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V5_6 is
	port(DInA        : in  std_logic;
	     DInB        : in  std_logic;
	     TDOut       : out std_logic;
		 IDOut       : out std_logic);
end V5_6;

architecture behav of V5_6 is
		
begin
	
	IDOut <= DInA and DInB after 10 ns;
	TDOut <= transport (DInA and DInB) after 10 ns;
	
end behav;