v8_7.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_7 is
    port(D   : in  std_logic;
         Q   : out std_logic := '0';
         Rst : in  std_logic;
         Clk : in  std_logic);
end V8_7;

architecture ARDFF of V8_7 is
begin
    process(Rst,Clk)
    begin
        if Rst = '0' then
            Q <= '0';
        elsif Clk = '1' and Clk'event then 
            Q <= D;
        end if;
    end process;
end ARDFF; 

architecture SRDFF of V8_7 is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            if Rst = '0' then
                Q <= '0';
            else 
                Q <= D;
            end if;
        end if;
    end process;
end SRDFF;

configuration CFG_DFF of V8_7 is 
    for ARDFF
    end for;
end CFG_DFF;